Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp

[Kito Cheng <kito.cheng@gmail.com>]

Only a few minor comments, otherwise LGTM :)

But I guess we need to wait until binutils merge zc stuff.

> Zcmp can share the same logic as save-restore in stack allocation: pre-allocation
> by cm.push, step 1 and step 2.
>
> please be noted cm.push pushes ra, s0-s11 in reverse order than what save-restore does.
> So adaption has been done in .cfi directives in my patch.
>
> Signed-off-by: Fei Gao <gaofei@eswincomputing.com>
>
> gcc/ChangeLog:
>
>         * config/riscv/iterators.md (-8): slot offset in bytes
>         (-16): likewise
>         (-24): likewise
>         (-32): likewise
>         (-40): likewise
>         (-48): likewise
>         (-56): likewise
>         (-64): likewise
>         (-72): likewise
>         (-80): likewise
>         (-88): likewise
>         (-96): likewise
>         (-104): likewise

Use slot0_offset...slot12_offset.

> @@ -422,6 +430,16 @@ static const struct riscv_tune_info riscv_tune_info_table[] = {
>  #include "riscv-cores.def"
>  };
>
> +typedef enum
> +{
> +  PUSH_IDX = 0,
> +  POP_IDX,
> +  POPRET_IDX,
> +  ZCMP_OP_NUM
> +} op_idx;

op_idx -> riscv_zcmp_op_t
> @@ -5388,6 +5487,42 @@ riscv_adjust_libcall_cfi_prologue ()
>    return dwarf;
>  }
>
> +static rtx
> +riscv_adjust_multi_push_cfi_prologue (int saved_size)
> +{
> +  rtx dwarf = NULL_RTX;
> +  rtx adjust_sp_rtx, reg, mem, insn;
> +  unsigned int mask = cfun->machine->frame.mask;
> +  int offset;
> +  int saved_cnt = 0;
> +
> +  if (mask & S10_MASK)
> +    mask |= S11_MASK;
> +
> +  for (int regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
> +    if (BITSET_P (mask & MULTI_PUSH_GPR_MASK, regno - GP_REG_FIRST))
> +      {
> +        /* The save order is s11-s0, ra
> +           from high to low addr.  */
> +        offset = saved_size - UNITS_PER_WORD * (++saved_cnt);
> +
> +        reg = gen_rtx_REG (SImode, regno);

Should be Pmode rather than SImode, and seems
riscv_adjust_libcall_cfi_prologue has same issue...could you send a
separate patch to fix that?

> +        mem = gen_frame_mem (SImode, plus_constant (Pmode,

Same here.

> +                                                    stack_pointer_rtx,
> +                                                    offset));
> +
> +        insn = gen_rtx_SET (mem, reg);
> +        dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf);
> +      }
> +
> +  /* Debug info for adjust sp.  */
> +  adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx,
> +                               plus_constant(Pmode, stack_pointer_rtx, -saved_size));
> +  dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> +                          dwarf);
> +  return dwarf;
> +}
> +
>  static void
>  riscv_emit_stack_tie (void)
>  {


> @@ -5493,6 +5697,32 @@ riscv_expand_prologue (void)
>      }
>  }
>
> +static rtx
> +riscv_adjust_multi_pop_cfi_epilogue (int saved_size)
> +{
> +  rtx dwarf = NULL_RTX;
> +  rtx adjust_sp_rtx, reg;
> +  unsigned int mask = cfun->machine->frame.mask;
> +
> +  if (mask & S10_MASK)
> +    mask |= S11_MASK;
> +
> +  /* Debug info for adjust sp.  */
> +  adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx,
> +                               plus_constant(Pmode, stack_pointer_rtx, saved_size));
> +  dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> +                          dwarf);
> +
> +  for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
> +    if (BITSET_P (mask, regno - GP_REG_FIRST))
> +      {
> +        reg = gen_rtx_REG (SImode, regno);

Pmode

> +        dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
> +      }
> +
> +  return dwarf;
> +}
> +
>  static rtx
>  riscv_adjust_libcall_cfi_epilogue ()
>  {

> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> new file mode 100644
> index 00000000000..f2f2198598c
> --- /dev/null
> +++ b/gcc/config/riscv/zc.md
> @@ -0,0 +1,1042 @@
> +;; Machine description for RISC-V Zc extention.
> +;; Copyright (C) 2011-2023 Free Software Foundation, Inc.

2023 rather than 2011-2023