From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by sourceware.org (Postfix) with ESMTPS id 5396838582B0 for ; Mon, 5 Jun 2023 08:31:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5396838582B0 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-xf2e.google.com with SMTP id 6a1803df08f44-62614a2ce61so40880576d6.3 for ; Mon, 05 Jun 2023 01:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685953900; x=1688545900; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=kI4JZoGJfku+nMqXMvQFRfFA3184VYH0f/mlU/2BsWY=; b=KyZkF+nsoj0ZwE/Efo4s4LwvJapH+jbwKhwcF5wh00DQ1PUJvqw4qJt0tK4QL99Bll bkvfk1B0Ngeqzh4kJSVhQYQRcvsdXKckMbn5lGDDuWvKLBSls+/QdZgCw9DlGBUfx6g0 WU59VdT8OeZ/LdYeCwv0q4qoYe4/cq5F3428MSOmYLpFMmUrX3kHjjOZurSPVbs6moG5 dIDqfE+pdiD5CJMV9SS+t02BFnHeVWf7CCiqrkjyf/U45aeqsr6j0JurA882JLA2aEG6 zT9WProODJQfHig/DRfTRs/ygdZnKmLgYscW98Oblw4VIMRrgOWTjyWmZFm9PLLlUdu1 ndEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685953900; x=1688545900; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=kI4JZoGJfku+nMqXMvQFRfFA3184VYH0f/mlU/2BsWY=; b=jr0xfT4IggB7lWi9Rfu/UUDOOfu1Xx3dydes7HEaVZRjnuJF1cRfqQ4AOpGExTNX1C iUvCwR8ZE+ZH4cw1f++UqVuWgpY6IQTcRV0RZQISM2caFN5LKDED+EZDarGWNWiIyN50 eJeC/Rf4QhUU6sTh7KW5ApgfLsLzty5HOSrANHM8pcfYgLoTCIys80+Ryd1OHdtq7A5m T9iq9wV0ocp+f1xBATHJTvpFAcdY0/P/ZxM88RRxcW8RPDH05XKaAhXaqaXRa5qg4D5v 1vWCTjKXQwa5XgzVABt3ZssRuHQjAxFytMNyC+TQRl2ckSC7B1uKN5PX49ppAfvkkmm0 /0JA== X-Gm-Message-State: AC+VfDyGoLZCRDkbJcM2SUGCfoNf/niSa/Lo0mE0jv9WIoWMRgA/00UP 79rkXtbkcx0jDQMTE6bFFHP4u0NnQ36U+vhznyA= X-Google-Smtp-Source: ACHHUZ7LwBfBglqW11WVsyy4pz7JWCTUZUL1mUixU17H9k/uM+GyF71+FxlyckQMFr36uhYbqUVZC8SELwM4iJxC0/A= X-Received: by 2002:a05:6214:27c9:b0:626:476:5e8c with SMTP id ge9-20020a05621427c900b0062604765e8cmr5465724qvb.52.1685953900459; Mon, 05 Jun 2023 01:31:40 -0700 (PDT) MIME-Version: 1.0 References: <20230602104247.26454-1-gaofei@eswincomputing.com> <20230602104247.26454-2-gaofei@eswincomputing.com> In-Reply-To: <20230602104247.26454-2-gaofei@eswincomputing.com> From: Kito Cheng Date: Mon, 5 Jun 2023 16:31:29 +0800 Message-ID: Subject: Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp To: Fei Gao Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com, jeffreyalaw@gmail.com, sinan.lin@linux.alibaba.com, jiawei@iscas.ac.cn Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Only a few minor comments, otherwise LGTM :) But I guess we need to wait until binutils merge zc stuff. > Zcmp can share the same logic as save-restore in stack allocation: pre-allocation > by cm.push, step 1 and step 2. > > please be noted cm.push pushes ra, s0-s11 in reverse order than what save-restore does. > So adaption has been done in .cfi directives in my patch. > > Signed-off-by: Fei Gao > > gcc/ChangeLog: > > * config/riscv/iterators.md (-8): slot offset in bytes > (-16): likewise > (-24): likewise > (-32): likewise > (-40): likewise > (-48): likewise > (-56): likewise > (-64): likewise > (-72): likewise > (-80): likewise > (-88): likewise > (-96): likewise > (-104): likewise Use slot0_offset...slot12_offset. > @@ -422,6 +430,16 @@ static const struct riscv_tune_info riscv_tune_info_table[] = { > #include "riscv-cores.def" > }; > > +typedef enum > +{ > + PUSH_IDX = 0, > + POP_IDX, > + POPRET_IDX, > + ZCMP_OP_NUM > +} op_idx; op_idx -> riscv_zcmp_op_t > @@ -5388,6 +5487,42 @@ riscv_adjust_libcall_cfi_prologue () > return dwarf; > } > > +static rtx > +riscv_adjust_multi_push_cfi_prologue (int saved_size) > +{ > + rtx dwarf = NULL_RTX; > + rtx adjust_sp_rtx, reg, mem, insn; > + unsigned int mask = cfun->machine->frame.mask; > + int offset; > + int saved_cnt = 0; > + > + if (mask & S10_MASK) > + mask |= S11_MASK; > + > + for (int regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) > + if (BITSET_P (mask & MULTI_PUSH_GPR_MASK, regno - GP_REG_FIRST)) > + { > + /* The save order is s11-s0, ra > + from high to low addr. */ > + offset = saved_size - UNITS_PER_WORD * (++saved_cnt); > + > + reg = gen_rtx_REG (SImode, regno); Should be Pmode rather than SImode, and seems riscv_adjust_libcall_cfi_prologue has same issue...could you send a separate patch to fix that? > + mem = gen_frame_mem (SImode, plus_constant (Pmode, Same here. > + stack_pointer_rtx, > + offset)); > + > + insn = gen_rtx_SET (mem, reg); > + dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf); > + } > + > + /* Debug info for adjust sp. */ > + adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx, > + plus_constant(Pmode, stack_pointer_rtx, -saved_size)); > + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, > + dwarf); > + return dwarf; > +} > + > static void > riscv_emit_stack_tie (void) > { > @@ -5493,6 +5697,32 @@ riscv_expand_prologue (void) > } > } > > +static rtx > +riscv_adjust_multi_pop_cfi_epilogue (int saved_size) > +{ > + rtx dwarf = NULL_RTX; > + rtx adjust_sp_rtx, reg; > + unsigned int mask = cfun->machine->frame.mask; > + > + if (mask & S10_MASK) > + mask |= S11_MASK; > + > + /* Debug info for adjust sp. */ > + adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx, > + plus_constant(Pmode, stack_pointer_rtx, saved_size)); > + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, > + dwarf); > + > + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) > + if (BITSET_P (mask, regno - GP_REG_FIRST)) > + { > + reg = gen_rtx_REG (SImode, regno); Pmode > + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); > + } > + > + return dwarf; > +} > + > static rtx > riscv_adjust_libcall_cfi_epilogue () > { > diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md > new file mode 100644 > index 00000000000..f2f2198598c > --- /dev/null > +++ b/gcc/config/riscv/zc.md > @@ -0,0 +1,1042 @@ > +;; Machine description for RISC-V Zc extention. > +;; Copyright (C) 2011-2023 Free Software Foundation, Inc. 2023 rather than 2011-2023