From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa36.google.com (mail-vk1-xa36.google.com [IPv6:2607:f8b0:4864:20::a36]) by sourceware.org (Postfix) with ESMTPS id 07AAB3858C2F for ; Thu, 27 Jul 2023 11:55:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 07AAB3858C2F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa36.google.com with SMTP id 71dfb90a1353d-48651709fa5so295194e0c.1 for ; Thu, 27 Jul 2023 04:55:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690458950; x=1691063750; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=lqwBUC1ILKMSxBn8DQQh/xAufAy8gEtmNxUmaQ5ODZE=; b=XNhZULdrEcxnMBnypumVS2r2/eUNCA/uzGXZcz2HpQSz+xhGnmUGpi1rmRZORXPul7 rZfRAPxWJ5uA8uq3xov4eUnC+mfpFZStNyOc98Ibl85c7MRh7RcU9fMnWk8/TCMwkTIL MFaAZUJmzv09Nf4nDcmQe6+BXg7gIFLdpdINqAX5f4EpXZK4sGXsqOGS/tIzE3HcglYC oZuNJuhk4Br5kjncqJ17NEF/4diKzqZ5XzJHOrtfzTW3JkZ0auILLcW4YB3YDi4/+yLf QVRMXneV9BISHwiHUnUHZUE6tm/UW1gmFo1UIyR/rNWID9oNso12ntiM6JNqcxqZCEaY csfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690458950; x=1691063750; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lqwBUC1ILKMSxBn8DQQh/xAufAy8gEtmNxUmaQ5ODZE=; b=Fx35suwy7bF/H3LzoMdjr7Dumrl3qjljPfmRoFXvzD1g1+fWlShw7P4XT38y9IBH5J pfLSTKT7CGhX4aTAd+6cmDri5WlB5/a0/C8F/yDPvrYYwFlL/nApOUAhrJV/DQ07c4Sm sfUEmppkUUKJmcvnA992Iiti+I5vDUqibgpjtSGvfYLfSWRQMO90WxD9dwulvpHzxocO cbuM5wBCtQ+MhAwDo2Ra8BFnLb4AZtBUlneIFwo6rq0UKA3exWOb14NUJ2em/djo5zoJ die11fzDZWfibfTW9WVrYam5/veZlD8K7p8d66aYoEAciSHTjj7YAB/Dm/erlVdlRAJU qiiw== X-Gm-Message-State: ABy/qLYJqD7ugJPANQT9Zn0CdZxq2hggdTPUtOsq2Tb3nXL4iwL5t5nA 7sRc21H2ApIIIvqlSRI7dqtberNWlSZD/vT8eQo= X-Google-Smtp-Source: APBJJlHM+kYq3JvtLU1F7qyUwl6mrxjqEWmh3rQeVJC43c+Q2fdqnFtYnClwmlQ+5KVoU1ZBYR12Oftpc4hCJJwHQ8Q= X-Received: by 2002:a1f:bdcc:0:b0:481:3721:7811 with SMTP id n195-20020a1fbdcc000000b0048137217811mr1184945vkf.0.1690458950116; Thu, 27 Jul 2023 04:55:50 -0700 (PDT) MIME-Version: 1.0 References: <1c9281b7-b1ee-82e9-fbbb-9a7e00d475bf@gmail.com> In-Reply-To: <1c9281b7-b1ee-82e9-fbbb-9a7e00d475bf@gmail.com> From: Kito Cheng Date: Thu, 27 Jul 2023 19:55:38 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. To: Jeff Law Cc: Robin Dapp , gcc-patches , palmer , "juzhe.zhong@rivai.ai" , vineetg@rivosinc.com, "Li, Pan2" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, I just found this patch still on the list, I mostly tested with qemu, so I don't think that is a problem before, but I realize it's a problem when we run on a real board that does not support those extensions. On Sun, Jun 18, 2023 at 6:07=E2=80=AFAM Jeff Law via Gcc-patches wrote: > > > > On 6/15/23 09:06, Robin Dapp wrote: > > Hi, > > > > Changes from v1: > > - Revamped the target selectors again. > > - Fixed some syntax as well as caching errors that were still present= . > > - Adjusted some test cases I missed. > > > > The current situation with target selectors is improvable at best. > > We definitely need to discern between being able to build a > > test with the current configuration and running the test on the > > current target which this patch attempts to do. There might > > be a need for more fine-grained checks in the future that could > > also go into our target-specific riscv.exp in the subdirectories > > but for now I think we're good. > > > > A bit more detail is in the patch description below. The testsuite > > is as clean as before for the configurations I tried: default, rv64gcv, > > rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin. I hope I didn't > > overlook tests that appear unsupported now but shouldn't be. > > > > @Pan: No need to check the old version anymore, thanks. This patch > > is preferred. > > > > Regards > > Robin > > > > > > This introduces new checks for run tests. Currently we have > > riscv_vector as well as rv32 and rv64 which all check if GCC (with the > > current configuration) can build the respective tests. > > > > Many tests specify e.g. a different -march for vector which > > makes the check fail even though we could build as well as run > > those tests. > > > > vector_hw now tries to compile, link and execute a simple vector exampl= e > > file. If this succeeds the respective test can run. > > > > Similarly we introduce a zvfh_hw check which will be used in the > > upcoming floating-point unop/binop tests as well as rv32_hw and > > rv64_hw checks that are currently unused. > > > > To conclude: > > - If we want a testcase to only compile when the current configuratio= n > > has vector support we use {riscv_vector}. > > - If we want a testcase to run when the current target can supports > > executing vector instructions we use {riscv_vector_hw}. > > It still needs to be ensured that we can actually build the test > > which can be achieved by either > > (1) compiling with e.g. -march=3Drv64gcv or > > (2) only enabling the test when the current configuration supports > > vector via {riscsv_vector}. > > > > The same principle applies for zfh, zfhmin and zvfh but we do not yet > > have all target selectors. In the meanwhile we need to make sure to > > specify the proper -march flags like in (1). > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use > > riscv_vector_hw. > > * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito. > > * gcc.target/riscv/rvv/autovec/series_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run= -1.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run= -2.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run= -3.c: > > Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito. > > * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use. > > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use. > > * g++.target/riscv/rvv/base/bug-10.C: Use. > > * g++.target/riscv/rvv/base/bug-11.C: Use. > > * g++.target/riscv/rvv/base/bug-12.C: Use. > > * g++.target/riscv/rvv/base/bug-13.C: Use. > > * g++.target/riscv/rvv/base/bug-14.C: Use. > > * g++.target/riscv/rvv/base/bug-15.C: Use. > > * g++.target/riscv/rvv/base/bug-16.C: Use. > > * g++.target/riscv/rvv/base/bug-17.C: Use. > > * g++.target/riscv/rvv/base/bug-2.C: Use. > > * g++.target/riscv/rvv/base/bug-23.C: Use. > > * g++.target/riscv/rvv/base/bug-3.C: Use. > > * g++.target/riscv/rvv/base/bug-4.C: Use. > > * g++.target/riscv/rvv/base/bug-5.C: Use. > > * g++.target/riscv/rvv/base/bug-6.C: Use. > > * g++.target/riscv/rvv/base/bug-7.C: Use. > > * g++.target/riscv/rvv/base/bug-8.C: Use. > > * g++.target/riscv/rvv/base/bug-9.C: Use. > > * lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw > > and zfh_hw, zfhmin_hw, zvfh_hw checks. > I'm OK with the basic idea here and the dejagnu bits look reasonable. > So I think the only question is whether or not others agree with the > basic direction on the testsuite. > > So let's give the other RISC-V contributors a couple days to chime in. > > Jeff