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References: <20230131130650.322631-1-juzhe.zhong@rivai.ai>
In-Reply-To: <20230131130650.322631-1-juzhe.zhong@rivai.ai>
From: Kito Cheng <kito.cheng@gmail.com>
Date: Wed, 1 Feb 2023 00:49:55 +0800
Message-ID: <CA+yXCZBUP5n_1UehDD9sD3KHnzUwCwvLm=2EQDPa2hM713a3rg@mail.gmail.com>
Subject: Re: [PATCH] RISC-V: Add vmin*.vv C++ API tests
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com
Content-Type: text/plain; charset="UTF-8"
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List-Id: <gcc-patches.gcc.gnu.org>

committed, thanks!

On Tue, Jan 31, 2023 at 9:07 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * g++.target/riscv/rvv/base/vmin_vv-1.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv-2.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv-3.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_mu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_mu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_mu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tu-3.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tum-1.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tum-2.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tum-3.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tumu-1.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tumu-2.C: New test.
>         * g++.target/riscv/rvv/base/vmin_vv_tumu-3.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv-1.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv-2.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv-3.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_mu-1.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_mu-2.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_mu-3.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tu-1.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tu-2.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tu-3.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tum-1.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tum-2.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tum-3.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tumu-1.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tumu-2.C: New test.
>         * g++.target/riscv/rvv/base/vminu_vv_tumu-3.C: New test.
>
> ---
>  .../g++.target/riscv/rvv/base/vmin_vv-1.C     | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv-2.C     | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv-3.C     | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_mu-1.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_mu-2.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_mu-3.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_tu-1.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_tu-2.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_tu-3.C  | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_tum-1.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_tum-2.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vmin_vv_tum-3.C | 160 +++++++++
>  .../riscv/rvv/base/vmin_vv_tumu-1.C           | 160 +++++++++
>  .../riscv/rvv/base/vmin_vv_tumu-2.C           | 160 +++++++++
>  .../riscv/rvv/base/vmin_vv_tumu-3.C           | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv-1.C    | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv-2.C    | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv-3.C    | 314 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv_mu-1.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv_mu-2.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv_mu-3.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv_tu-1.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv_tu-2.C | 160 +++++++++
>  .../g++.target/riscv/rvv/base/vminu_vv_tu-3.C | 160 +++++++++
>  .../riscv/rvv/base/vminu_vv_tum-1.C           | 160 +++++++++
>  .../riscv/rvv/base/vminu_vv_tum-2.C           | 160 +++++++++
>  .../riscv/rvv/base/vminu_vv_tum-3.C           | 160 +++++++++
>  .../riscv/rvv/base/vminu_vv_tumu-1.C          | 160 +++++++++
>  .../riscv/rvv/base/vminu_vv_tumu-2.C          | 160 +++++++++
>  .../riscv/rvv/base/vminu_vv_tumu-3.C          | 160 +++++++++
>  30 files changed, 5724 insertions(+)
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-3.C
>
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-1.C
> new file mode 100644
> index 00000000000..1e741779d04
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-1.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,vl);
> +}
> +
> +
> +vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-2.C
> new file mode 100644
> index 00000000000..e212ffaad99
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-2.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,31);
> +}
> +
> +
> +vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-3.C
> new file mode 100644
> index 00000000000..6f2aca74c79
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-3.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(op1,op2,32);
> +}
> +
> +
> +vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-1.C
> new file mode 100644
> index 00000000000..efad12aac7c
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-2.C
> new file mode 100644
> index 00000000000..c51a7dd7cfb
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-3.C
> new file mode 100644
> index 00000000000..44573bcc105
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-1.C
> new file mode 100644
> index 00000000000..2e7d7dbf850
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-2.C
> new file mode 100644
> index 00000000000..a42db0a0547
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-3.C
> new file mode 100644
> index 00000000000..8d7a0d1b7f0
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-1.C
> new file mode 100644
> index 00000000000..8e3e5bf8ece
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-2.C
> new file mode 100644
> index 00000000000..652872866d3
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-3.C
> new file mode 100644
> index 00000000000..f938bf5d8ed
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-1.C
> new file mode 100644
> index 00000000000..cb9c7cec204
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-2.C
> new file mode 100644
> index 00000000000..0188e69b974
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-3.C
> new file mode 100644
> index 00000000000..b4ef03f2d20
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-1.C
> new file mode 100644
> index 00000000000..dbe3b849391
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-1.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vminu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-2.C
> new file mode 100644
> index 00000000000..13ebe5bdbd8
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-2.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vminu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-3.C
> new file mode 100644
> index 00000000000..f3373968f70
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-3.C
> @@ -0,0 +1,314 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vminu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-1.C
> new file mode 100644
> index 00000000000..dac489d2830
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-2.C
> new file mode 100644
> index 00000000000..19621e61134
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-3.C
> new file mode 100644
> index 00000000000..db40ebd059a
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-1.C
> new file mode 100644
> index 00000000000..f479436d484
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-2.C
> new file mode 100644
> index 00000000000..1c796bd5048
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-3.C
> new file mode 100644
> index 00000000000..349a7daa205
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-1.C
> new file mode 100644
> index 00000000000..89b91a360c2
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-2.C
> new file mode 100644
> index 00000000000..646c73b6725
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-3.C
> new file mode 100644
> index 00000000000..4e3724e2373
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-1.C
> new file mode 100644
> index 00000000000..525b42f85c5
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-1.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-2.C
> new file mode 100644
> index 00000000000..9c4b27ac84d
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-2.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-3.C
> new file mode 100644
> index 00000000000..b9d646674a4
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-3.C
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
> --
> 2.36.3
>