From: Kito Cheng <kito.cheng@gmail.com>
To: jiawei <jiawei@iscas.ac.cn>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Christoph Muellner <cmuellner@ventanamicro.com>,
Andrew Waterman <andrew@sifive.com>,
sinan <sinan@isrc.iscas.ac.cn>,
tariq.kurd=huawei.com@lists.riscv.org,
Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH 1/3] RISC-V: Minimal support of zfinx extension
Date: Thu, 4 Nov 2021 23:04:05 +0800 [thread overview]
Message-ID: <CA+yXCZBUZcD_03WuZqkbCUsp7+7Hp_182=TD52CRFf6SxHp52w@mail.gmail.com> (raw)
In-Reply-To: <20211028135246.9699-2-jiawei@iscas.ac.cn>
Could you add the information about zdinx implied zfinx to riscv_implied_info_t?
Thanks!
On Thu, Oct 28, 2021 at 9:56 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
> ---
> gcc/common/config/riscv/riscv-common.c | 6 ++++++
> gcc/config/riscv/riscv-opts.h | 6 ++++++
> gcc/config/riscv/riscv.opt | 3 +++
> 3 files changed, 15 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
> index 37b6ea80086..ab48909e338 100644
> --- a/gcc/common/config/riscv/riscv-common.c
> +++ b/gcc/common/config/riscv/riscv-common.c
> @@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
>
> + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
> +
> /* Terminate the list. */
> {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> };
> @@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
> {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
>
> + {"zfinx", &gcc_options::x_riscv_zf_subext, MASK_ZFINX},
> + {"zdinx", &gcc_options::x_riscv_zf_subext, MASK_ZDINX},
> +
> {NULL, NULL, 0}
> };
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 2efc4b80f1f..5a790a028cf 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -83,4 +83,10 @@ enum stack_protector_guard {
> #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
> #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
>
> +#define MASK_ZFINX (1 << 0)
> +#define MASK_ZDINX (1 << 1)
> +
> +#define TARGET_ZFINX ((riscv_zf_subext & MASK_ZFINX) != 0)
> +#define TARGET_ZDINX ((riscv_zf_subext & MASK_ZDINX) != 0)
> +
> #endif /* ! GCC_RISCV_OPTS_H */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 15bf89e17c2..54d27747eff 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -198,6 +198,9 @@ int riscv_zi_subext
> TargetVariable
> int riscv_zb_subext
>
> +TargetVariable
> +int riscv_zf_subext
> +
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-11-04 15:04 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 13:52 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
2021-10-28 13:52 ` [PATCH 1/3] RISC-V: Minimal support of zfinx extension jiawei
2021-11-04 15:04 ` Kito Cheng [this message]
2021-10-28 13:52 ` [PATCH 2/3] RISC-V: Target support for " jiawei
2021-10-28 13:52 ` [PATCH 3/3] RISC-V: Imply info and regs limit " jiawei
2021-11-04 14:59 ` Kito Cheng
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