From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe34.google.com (mail-vs1-xe34.google.com [IPv6:2607:f8b0:4864:20::e34]) by sourceware.org (Postfix) with ESMTPS id 6484E3858438 for ; Fri, 27 Jan 2023 09:36:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6484E3858438 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe34.google.com with SMTP id t10so4729718vsr.3 for ; Fri, 27 Jan 2023 01:36:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=r3LuY8rSPgKT127OwNxoaeKVLn6w2qF5efz0x7J1CoI=; b=eOWICF/9ztjfyGyz7GY1Sx8gHZ/JbO6YaucEhhd2ldsqIK1nVMJMRZKKE1l24tYztf VJ94vKr6YKcYjSR+NMuJGrVwG+2VfLCzA9PxD7yZLTN8ZqBmVnXSGu2JGsuX5cSLeqpj z6pITWy7GsYeeIuns7Bp/04IunqhnIE3FN/1VOJPviVNiMUcvJDE8cxXY8IzkQQfkxBK u7CGvnGLqaqSKZDhEt7s9u0+AsiV2wEVn7WEbvgfEKuRWCpSYedWiTrGP0BdNonEW038 czwgCsO9XeT7Lnw3co6WtQSU8IrxakR9x4Vs2sWysYsKmQ3JjMH9+z1uGInR/NZwyb1m I7Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=r3LuY8rSPgKT127OwNxoaeKVLn6w2qF5efz0x7J1CoI=; b=FrcwJVJ1RF2fpXy5bIPHyb0BibVdgJaVkf+r68RVz0N3xnmafTf1+P/aW3whC/t+HE wiFbun5bB80x14acxaa8Zoa7RYBuqzNnGIujDFNJN/betfqL7ZgJbHTXgeBwHPuzKFiS ssbzPLxmdqlijCHlzgAR2Wh3/snoTt6cyA55+bWjr5ht79cQgf2SoQguADqr0yyOh+wy bpyBNaHl/IqTF/YnNhDTYQVtgGTvPSPg9XrW1dYL01gWwXkmU6w2PoCtoDqSzPLXxoQw Awa3HUj7orT7mVcjkkMcesYhA6hqGNzcMYQUFuW49RgdQ6tA6Y2h+LKgYSXB4yfc3irH zD6w== X-Gm-Message-State: AFqh2kryD7WUCgCD2KDxz7KorSMeD8nz7GcxWkU1MLWdCtfub6fu7vMY SEGUlRfzilJFPv8fjzph+5Xcaln5WezMljOvhNE= X-Google-Smtp-Source: AMrXdXuUV6dmJA7AZJxst5/V3+CqbnIHpyc+g37plhoviUdLLfZnRO81eC0i0FK9dQSP4CvAWQaKY7gBqIVJPICEEhk= X-Received: by 2002:a05:6102:d2:b0:3ce:fc17:8836 with SMTP id u18-20020a05610200d200b003cefc178836mr5005043vsp.71.1674812163592; Fri, 27 Jan 2023 01:36:03 -0800 (PST) MIME-Version: 1.0 References: <20230118024415.64340-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230118024415.64340-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 27 Jan 2023 17:35:52 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix incorrect attributes of vsetvl instructions pattern To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: multipart/alternative; boundary="00000000000013957e05f33b98a9" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000013957e05f33b98a9 Content-Type: text/plain; charset="UTF-8" committed, thanks! On Wed, Jan 18, 2023 at 10:44 AM wrote: > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/vector.md: Fix incorrect attributes. > > --- > gcc/config/riscv/vector.md | 27 ++++++++++++--------------- > 1 file changed, 12 insertions(+), 15 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 4e93b7fead5..37cf4d6bcbf 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -95,13 +95,7 @@ > (const_int 32) > (eq_attr "mode" "VNx1DI,VNx2DI,VNx4DI,VNx8DI,\ > VNx1DF,VNx2DF,VNx4DF,VNx8DF") > - (const_int 64) > - > - (eq_attr "type" "vsetvl") > - (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi > - || INSN_CODE (curr_insn) == > CODE_FOR_vsetvlsi") > - (symbol_ref "INTVAL (operands[2])") > - (const_int INVALID_ATTRIBUTE))] > + (const_int 64)] > (const_int INVALID_ATTRIBUTE))) > > ;; Ditto to LMUL. > @@ -149,12 +143,7 @@ > (eq_attr "mode" "VNx4DI,VNx4DF") > (symbol_ref "riscv_vector::get_vlmul(E_VNx4DImode)") > (eq_attr "mode" "VNx8DI,VNx8DF") > - (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)") > - (eq_attr "type" "vsetvl") > - (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi > - || INSN_CODE (curr_insn) == > CODE_FOR_vsetvlsi") > - (symbol_ref "INTVAL (operands[3])") > - (const_int INVALID_ATTRIBUTE))] > + (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)")] > (const_int INVALID_ATTRIBUTE))) > > ;; It is valid for instruction that require sew/lmul ratio. > @@ -531,7 +520,11 @@ > "TARGET_VECTOR" > "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5" > [(set_attr "type" "vsetvl") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "sew") (symbol_ref "INTVAL (operands[2])")) > + (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])")) > + (set (attr "ta") (symbol_ref "INTVAL (operands[4])")) > + (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))]) > > ;; vsetvl zero,zero,vtype instruction. > ;; This pattern has no side effects and does not set X0 register. > @@ -563,7 +556,11 @@ > "TARGET_VECTOR" > "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4" > [(set_attr "type" "vsetvl") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "sew") (symbol_ref "INTVAL (operands[1])")) > + (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])")) > + (set (attr "ta") (symbol_ref "INTVAL (operands[3])")) > + (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))]) > > ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects. > ;; Since we have many optmization passes from "expand" to > "reload_completed", > -- > 2.36.3 > > --00000000000013957e05f33b98a9--