Lgtm Pan Li via Gcc-patches 於 2023年8月17日 週四，11:09寫道： > From: Pan Li > > This patch would like to support the rounding mode API for the > VFREDUSUM.VS as the below samples. > > * __riscv_vfredusum_vs_f32m1_f32m1_rm > * __riscv_vfredusum_vs_f32m1_f32m1_rm_m > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-bases.cc > (class freducop): Add frm_op_type template arg. > (vfredusum_frm_obj): New declaration. > (BASE): Ditto. > * config/riscv/riscv-vector-builtins-bases.h: Ditto. > * config/riscv/riscv-vector-builtins-functions.def > (vfredusum_frm): New intrinsic function def. > * config/riscv/riscv-vector-builtins-shapes.cc > (struct reduc_alu_frm_def): New class for frm shape. > (SHAPE): New declaration. > * config/riscv/riscv-vector-builtins-shapes.h: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-redusum.c: New test. > --- > .../riscv/riscv-vector-builtins-bases.cc | 9 ++++- > .../riscv/riscv-vector-builtins-bases.h | 1 + > .../riscv/riscv-vector-builtins-functions.def | 2 + > .../riscv/riscv-vector-builtins-shapes.cc | 39 +++++++++++++++++++ > .../riscv/riscv-vector-builtins-shapes.h | 1 + > .../riscv/rvv/base/float-point-redusum.c | 33 ++++++++++++++++ > 6 files changed, 84 insertions(+), 1 deletion(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c > > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc > b/gcc/config/riscv/riscv-vector-builtins-bases.cc > index ad04647f9ba..65f1d9c8ff7 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc > @@ -1847,10 +1847,15 @@ public: > }; > > /* Implements floating-point reduction instructions. */ > -template > +template > class freducop : public function_base > { > public: > + bool has_rounding_mode_operand_p () const override > + { > + return FRM_OP == HAS_FRM; > + } > + > bool apply_mask_policy_p () const override { return false; } > > rtx expand (function_expander &e) const override > @@ -2532,6 +2537,7 @@ static CONSTEXPR const reducop vredxor_obj; > static CONSTEXPR const widen_reducop vwredsum_obj; > static CONSTEXPR const widen_reducop vwredsumu_obj; > static CONSTEXPR const freducop vfredusum_obj; > +static CONSTEXPR const freducop > vfredusum_frm_obj; > static CONSTEXPR const freducop vfredosum_obj; > static CONSTEXPR const reducop vfredmax_obj; > static CONSTEXPR const reducop vfredmin_obj; > @@ -2789,6 +2795,7 @@ BASE (vredxor) > BASE (vwredsum) > BASE (vwredsumu) > BASE (vfredusum) > +BASE (vfredusum_frm) > BASE (vfredosum) > BASE (vfredmax) > BASE (vfredmin) > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h > b/gcc/config/riscv/riscv-vector-builtins-bases.h > index c8c649c4bb0..fd1a84f3e68 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-bases.h > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h > @@ -239,6 +239,7 @@ extern const function_base *const vredxor; > extern const function_base *const vwredsum; > extern const function_base *const vwredsumu; > extern const function_base *const vfredusum; > +extern const function_base *const vfredusum_frm; > extern const function_base *const vfredosum; > extern const function_base *const vfredmax; > extern const function_base *const vfredmin; > diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def > b/gcc/config/riscv/riscv-vector-builtins-functions.def > index cfbc125dcd8..90a83c02d52 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-functions.def > +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def > @@ -500,6 +500,8 @@ DEF_RVV_FUNCTION (vfredosum, reduc_alu, no_mu_preds, > f_vs_ops) > DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds, f_vs_ops) > DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops) > > +DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops) > + > // 14.4. Vector Widening Floating-Point Reduction Instructions > DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops) > DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops) > diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc > b/gcc/config/riscv/riscv-vector-builtins-shapes.cc > index 80329113af3..f8fdec863e6 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc > +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc > @@ -371,6 +371,44 @@ struct narrow_alu_frm_def : public build_frm_base > } > }; > > +/* reduc_alu_frm_def class. */ > +struct reduc_alu_frm_def : public build_frm_base > +{ > + char *get_name (function_builder &b, const function_instance &instance, > + bool overloaded_p) const override > + { > + char base_name[BASE_NAME_MAX_LEN] = {}; > + > + normalize_base_name (base_name, instance.base_name, sizeof > (base_name)); > + > + b.append_base_name (base_name); > + > + /* vop_ --> vop__. */ > + if (!overloaded_p) > + { > + b.append_name (operand_suffixes[instance.op_info->op]); > + b.append_name (type_suffixes[instance.type.index].vector); > + vector_type_index ret_type_idx > + = instance.op_info->ret.get_function_type_index > (instance.type.index); > + b.append_name (type_suffixes[ret_type_idx].vector); > + } > + > + /* According to rvv-intrinsic-doc, it does not add "_rm" suffix > + for vop_rm C++ overloaded API. */ > + if (!overloaded_p) > + b.append_name ("_rm"); > + > + /* According to rvv-intrinsic-doc, it does not add "_m" suffix > + for vop_m C++ overloaded API. */ > + if (overloaded_p && instance.pred == PRED_TYPE_m) > + return b.finish_name (); > + > + b.append_name (predication_suffixes[instance.pred]); > + > + return b.finish_name (); > + } > +}; > + > /* widen_alu_def class. Handle vwadd/vwsub. Unlike > vadd.vx/vadd.vv/vwmul.vv/vwmul.vx, vwadd.vv/vwadd.vx/vwadd.wv/vwadd.wx > has > 'OP' suffix in overloaded API. */ > @@ -898,6 +936,7 @@ SHAPE(narrow_alu_frm, narrow_alu_frm) > SHAPE(move, move) > SHAPE(mask_alu, mask_alu) > SHAPE(reduc_alu, reduc_alu) > +SHAPE(reduc_alu_frm, reduc_alu_frm) > SHAPE(scalar_move, scalar_move) > SHAPE(vundefined, vundefined) > SHAPE(misc, misc) > diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h > b/gcc/config/riscv/riscv-vector-builtins-shapes.h > index b53ab451902..92eb8bc9d71 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h > +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h > @@ -39,6 +39,7 @@ extern const function_shape *const narrow_alu_frm; > extern const function_shape *const move; > extern const function_shape *const mask_alu; > extern const function_shape *const reduc_alu; > +extern const function_shape *const reduc_alu_frm; > extern const function_shape *const scalar_move; > extern const function_shape *const vundefined; > extern const function_shape *const misc; > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c > new file mode 100644 > index 00000000000..36da6dd46f7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vfloat32m1_t > +test_riscv_vfredusum_vs_f32m1_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t > op2, > + size_t vl) { > + return __riscv_vfredusum_vs_f32m1_f32m1_rm (op1, op2, 0, vl); > +} > + > +vfloat32m1_t > +test_vfredusum_vs_f32m1_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, > + vfloat32m1_t op2, size_t vl) { > + return __riscv_vfredusum_vs_f32m1_f32m1_rm_m (mask, op1, op2, 1, vl); > +} > + > +vfloat32m1_t > +test_riscv_vfredusum_vs_f32m1_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, > + size_t vl) { > + return __riscv_vfredusum_vs_f32m1_f32m1 (op1, op2, vl); > +} > + > +vfloat32m1_t > +test_vfredusum_vs_f32m1_f32m1_m (vbool32_t mask, vfloat32m1_t op1, > + vfloat32m1_t op2, size_t vl) { > + return __riscv_vfredusum_vs_f32m1_f32m1_m (mask, op1, op2, vl); > +} > + > +/* { dg-final { scan-assembler-times {vfredusum\.vs\s+v[0-9]+,\s*v[0-9]+} > 4 } } */ > +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ > +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ > +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ > -- > 2.34.1 > >