From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by sourceware.org (Postfix) with ESMTPS id A7EAB384640E for ; Thu, 25 Apr 2024 03:19:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A7EAB384640E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A7EAB384640E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::233 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714015154; cv=none; b=sAnbDVXSrIMWGaxVe882ZCS1vGkuH3Upikj6KR5Rh01czt2O1+MBEzCHQsJBA27PEJ7ntSTOacJcogDmHcDXDh7h9sypofLtMcnH0maPeNO24ywTQjcQEoHTYwP3K6mPvNrItw7jfdMYX0fOJQgXmAYfMlxDpLYElC/6kuvWWPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714015154; c=relaxed/simple; bh=MLwS68doUOxpCe+XzQ7RKvCB8q3dnd5f29CQzhOHK5g=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=e3eA9PruoXMvZdwMTspmEmxZBMZHTji6lrvikTPIqh0wA6s2lFe8Cxlr3Ba0oo6eh7jUkw9bkYzMrMU0Awmn81JmT9FrfR67R6Xwd6+xHzAfm7jy04EY1R47+pLhVaMKpgYDYVz5dfRmyafwIm84gu/UjE82mbmdB5arxogNvW4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2dd6a7ae2dcso6530711fa.1 for ; Wed, 24 Apr 2024 20:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714015149; x=1714619949; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Qp5NoWsvk2Pf+P0LW8n/KgETTW8x2asYrT3aFTQoN34=; b=FwX1nsQpcW0TIFPLM1uJzTirBgEMuMZhJjjNl9og00GtLKKJSHv7PjXedVsKK6xHv7 fLJgFfNwZl02qrPMc3KptYKHppEs93AxAdTH5aVqu169cZWJN51yvxJmbj35SoQvlmpQ Zd8hq3IHWxWaU2Oi9xI7kusuWiqP3oJflca2IKl4qK66oItai0mIWgFDs92ZBEFpoGlF coWixfMYiPH12hfiW0fVWDxu/E4AKVO/mTuEPknrXVfA9s2nixMQW3+kjZRpTgKlovhV RXijDvzdHtyZ5NKD2QfiyHSVpKpkw6/d59Zcjj5uEjJyfcIHfuS0wW8scwHXaQRCs73l j8GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714015149; x=1714619949; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Qp5NoWsvk2Pf+P0LW8n/KgETTW8x2asYrT3aFTQoN34=; b=m4pBPyQyXcOrncfd3g7YtBO8SicsLPIsYmr8RoPtT57W3oVh1y4UwedFoAJ9lDkoIA uEByauiCGNRltbFbHhoVtFa25nThpnLbs3Anth/GbcTlKwPgbiM2RjQVLVtHZY7A66K/ IcRav9Q4+gne5KzlyvFYH1lOVCBQm7I03saRS1eWXzVMaIAvQL8H/rHnNZuIuh/XOGVP luneM29VAkjc1kcKrtrolDfj4N/dwB9feqeruABv2NXxA9DH5xgec5x5KGCDqXmRZAaV hBgNobE0QSrC0Rmrn//YcT2eYixd09h9qQaeq2X7gZxZDdcL+cUS+T85kCoDLhTjXKzv BJkg== X-Forwarded-Encrypted: i=1; AJvYcCXXznHSo37T8UNIz1ixYy4U563DbyJXp8zD46yjbxK8K/RMhPxEZcNUEDGvbr5UQ3u0eqMgZfxVC+cjQHNIbKUTE2gc/r/PKw== X-Gm-Message-State: AOJu0YygCo390Si8YEi2sqNsYoNaA8nM29hu0Ip2g+ogoVU05F/DaQEv gFRnSfzJKh53aW+F0vIvADPgcCqYtBKVHQhpUQp6sRrP3AX/XrcpFYPKo9GK/oyb9GSqCC2l5TG jTZQODunOjzKAdAInoaQqQVZZLcAtMw== X-Google-Smtp-Source: AGHT+IE8xCd/4NV5q7wb/omthjJO6gKVnw8nNCDYxEWzgaxvwJyBn+p2Pm9a0AO1oQb+4mIHN0uCjw/QoonXVw1s4qk= X-Received: by 2002:a2e:7d11:0:b0:2d8:6a04:3bcd with SMTP id y17-20020a2e7d11000000b002d86a043bcdmr3364482ljc.3.1714015148689; Wed, 24 Apr 2024 20:19:08 -0700 (PDT) MIME-Version: 1.0 References: <20240425012512.2079275-1-pan2.li@intel.com> In-Reply-To: From: Kito Cheng Date: Thu, 25 Apr 2024 11:18:56 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap of vwcvt To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: "pan2.li" , gcc-patches , Robin Dapp Content-Type: multipart/alternative; boundary="00000000000013d5210616e340c3" X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000013d5210616e340c3 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM juzhe.zhong@rivai.ai =E6=96=BC 2024=E5=B9=B44=E6=9C= =8825=E6=97=A5 =E9=80=B1=E5=9B=9B 09:26 =E5=AF=AB=E9=81=93=EF=BC=9A > lgtm > > ------------------------------ > juzhe.zhong@rivai.ai > > > *From:* pan2.li > *Date:* 2024-04-25 09:25 > *To:* gcc-patches > *CC:* juzhe.zhong ; kito.cheng > ; rdapp.gcc ; Pan Li > > *Subject:* [PATCH v1] RISC-V: Add xfail test case for highpart register > overlap of vwcvt > From: Pan Li > > We reverted below patch for register group overlap, add the related > insn test and mark it as xfail. And we will remove the xfail > after we support the register overlap in GCC-15. > > bdad036da32 RISC-V: Support highpart register overlap for vwcvt > > The below test suites are passed for this patch > * The rv64gcv fully regression test with isl build. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr112431-1.c: New test. > * gcc.target/riscv/rvv/base/pr112431-2.c: New test. > * gcc.target/riscv/rvv/base/pr112431-3.c: New test. > > Signed-off-by: Pan Li > --- > .../gcc.target/riscv/rvv/base/pr112431-1.c | 104 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/pr112431-2.c | 68 ++++++++++++ > .../gcc.target/riscv/rvv/base/pr112431-3.c | 51 +++++++++ > 3 files changed, 223 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c > new file mode 100644 > index 00000000000..6f9c6f7bd8c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c > @@ -0,0 +1,104 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ > + > +#include "riscv_vector.h" > + > +size_t __attribute__ ((noinline)) > +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum= 4, > + size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, > + size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, > + size_t sum15) > +{ > + return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + > sum9 > + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; > +} > + > +size_t > +foo (char const *buf, size_t len) > +{ > + size_t sum =3D 0; > + size_t vl =3D __riscv_vsetvlmax_e8m8 (); > + size_t step =3D vl * 4; > + const char *it =3D buf, *end =3D buf + len; > + for (; it + step <=3D end;) > + { > + vint8m1_t v0 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v1 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v2 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v3 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v4 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v5 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v6 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v7 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v8 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v9 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v10 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v11 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v12 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v13 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v14 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + vint8m1_t v15 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); > + it +=3D vl; > + > + asm volatile("nop" ::: "memory"); > + vint16m2_t vw0 =3D __riscv_vwcvt_x_x_v_i16m2 (v0, vl); > + vint16m2_t vw1 =3D __riscv_vwcvt_x_x_v_i16m2 (v1, vl); > + vint16m2_t vw2 =3D __riscv_vwcvt_x_x_v_i16m2 (v2, vl); > + vint16m2_t vw3 =3D __riscv_vwcvt_x_x_v_i16m2 (v3, vl); > + vint16m2_t vw4 =3D __riscv_vwcvt_x_x_v_i16m2 (v4, vl); > + vint16m2_t vw5 =3D __riscv_vwcvt_x_x_v_i16m2 (v5, vl); > + vint16m2_t vw6 =3D __riscv_vwcvt_x_x_v_i16m2 (v6, vl); > + vint16m2_t vw7 =3D __riscv_vwcvt_x_x_v_i16m2 (v7, vl); > + vint16m2_t vw8 =3D __riscv_vwcvt_x_x_v_i16m2 (v8, vl); > + vint16m2_t vw9 =3D __riscv_vwcvt_x_x_v_i16m2 (v9, vl); > + vint16m2_t vw10 =3D __riscv_vwcvt_x_x_v_i16m2 (v10, vl); > + vint16m2_t vw11 =3D __riscv_vwcvt_x_x_v_i16m2 (v11, vl); > + vint16m2_t vw12 =3D __riscv_vwcvt_x_x_v_i16m2 (v12, vl); > + vint16m2_t vw13 =3D __riscv_vwcvt_x_x_v_i16m2 (v13, vl); > + vint16m2_t vw14 =3D __riscv_vwcvt_x_x_v_i16m2 (v14, vl); > + vint16m2_t vw15 =3D __riscv_vwcvt_x_x_v_i16m2 (v15, vl); > + > + asm volatile("nop" ::: "memory"); > + size_t sum0 =3D __riscv_vmv_x_s_i16m2_i16 (vw0); > + size_t sum1 =3D __riscv_vmv_x_s_i16m2_i16 (vw1); > + size_t sum2 =3D __riscv_vmv_x_s_i16m2_i16 (vw2); > + size_t sum3 =3D __riscv_vmv_x_s_i16m2_i16 (vw3); > + size_t sum4 =3D __riscv_vmv_x_s_i16m2_i16 (vw4); > + size_t sum5 =3D __riscv_vmv_x_s_i16m2_i16 (vw5); > + size_t sum6 =3D __riscv_vmv_x_s_i16m2_i16 (vw6); > + size_t sum7 =3D __riscv_vmv_x_s_i16m2_i16 (vw7); > + size_t sum8 =3D __riscv_vmv_x_s_i16m2_i16 (vw8); > + size_t sum9 =3D __riscv_vmv_x_s_i16m2_i16 (vw9); > + size_t sum10 =3D __riscv_vmv_x_s_i16m2_i16 (vw10); > + size_t sum11 =3D __riscv_vmv_x_s_i16m2_i16 (vw11); > + size_t sum12 =3D __riscv_vmv_x_s_i16m2_i16 (vw12); > + size_t sum13 =3D __riscv_vmv_x_s_i16m2_i16 (vw13); > + size_t sum14 =3D __riscv_vmv_x_s_i16m2_i16 (vw14); > + size_t sum15 =3D __riscv_vmv_x_s_i16m2_i16 (vw15); > + > + sum +=3D sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, > sum8, > + sum9, sum10, sum11, sum12, sum13, sum14, sum15); > + } > + return sum; > +} > + > +/* { dg-final { scan-assembler-not {vmv1r} } } */ > +/* { dg-final { scan-assembler-not {vmv2r} } } */ > +/* { dg-final { scan-assembler-not {vmv4r} } } */ > +/* { dg-final { scan-assembler-not {vmv8r} } } */ > +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c > new file mode 100644 > index 00000000000..b99dd19e623 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ > + > +#include "riscv_vector.h" > + > +size_t __attribute__ ((noinline)) > +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum= 4, > + size_t sum5, size_t sum6, size_t sum7) > +{ > + return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; > +} > + > +size_t > +foo (char const *buf, size_t len) > +{ > + size_t sum =3D 0; > + size_t vl =3D __riscv_vsetvlmax_e8m8 (); > + size_t step =3D vl * 4; > + const char *it =3D buf, *end =3D buf + len; > + for (; it + step <=3D end;) > + { > + vint8m2_t v0 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v1 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v2 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v3 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v4 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v5 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v6 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + vint8m2_t v7 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); > + it +=3D vl; > + > + asm volatile("nop" ::: "memory"); > + vint16m4_t vw0 =3D __riscv_vwcvt_x_x_v_i16m4 (v0, vl); > + vint16m4_t vw1 =3D __riscv_vwcvt_x_x_v_i16m4 (v1, vl); > + vint16m4_t vw2 =3D __riscv_vwcvt_x_x_v_i16m4 (v2, vl); > + vint16m4_t vw3 =3D __riscv_vwcvt_x_x_v_i16m4 (v3, vl); > + vint16m4_t vw4 =3D __riscv_vwcvt_x_x_v_i16m4 (v4, vl); > + vint16m4_t vw5 =3D __riscv_vwcvt_x_x_v_i16m4 (v5, vl); > + vint16m4_t vw6 =3D __riscv_vwcvt_x_x_v_i16m4 (v6, vl); > + vint16m4_t vw7 =3D __riscv_vwcvt_x_x_v_i16m4 (v7, vl); > + > + asm volatile("nop" ::: "memory"); > + size_t sum0 =3D __riscv_vmv_x_s_i16m4_i16 (vw0); > + size_t sum1 =3D __riscv_vmv_x_s_i16m4_i16 (vw1); > + size_t sum2 =3D __riscv_vmv_x_s_i16m4_i16 (vw2); > + size_t sum3 =3D __riscv_vmv_x_s_i16m4_i16 (vw3); > + size_t sum4 =3D __riscv_vmv_x_s_i16m4_i16 (vw4); > + size_t sum5 =3D __riscv_vmv_x_s_i16m4_i16 (vw5); > + size_t sum6 =3D __riscv_vmv_x_s_i16m4_i16 (vw6); > + size_t sum7 =3D __riscv_vmv_x_s_i16m4_i16 (vw7); > + > + sum +=3D sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); > + } > + return sum; > +} > + > +/* { dg-final { scan-assembler-not {vmv1r} } } */ > +/* { dg-final { scan-assembler-not {vmv2r} } } */ > +/* { dg-final { scan-assembler-not {vmv4r} } } */ > +/* { dg-final { scan-assembler-not {vmv8r} } } */ > +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c > new file mode 100644 > index 00000000000..cac50bd003c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c > @@ -0,0 +1,51 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ > + > +#include "riscv_vector.h" > + > +size_t __attribute__ ((noinline)) > +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) > +{ > + return sum0 + sum1 + sum2 + sum3; > +} > + > +size_t > +foo (char const *buf, size_t len) > +{ > + size_t sum =3D 0; > + size_t vl =3D __riscv_vsetvlmax_e8m8 (); > + size_t step =3D vl * 4; > + const char *it =3D buf, *end =3D buf + len; > + for (; it + step <=3D end;) > + { > + vint8m4_t v0 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); > + it +=3D vl; > + vint8m4_t v1 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); > + it +=3D vl; > + vint8m4_t v2 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); > + it +=3D vl; > + vint8m4_t v3 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); > + it +=3D vl; > + > + asm volatile("nop" ::: "memory"); > + vint16m8_t vw0 =3D __riscv_vwcvt_x_x_v_i16m8 (v0, vl); > + vint16m8_t vw1 =3D __riscv_vwcvt_x_x_v_i16m8 (v1, vl); > + vint16m8_t vw2 =3D __riscv_vwcvt_x_x_v_i16m8 (v2, vl); > + vint16m8_t vw3 =3D __riscv_vwcvt_x_x_v_i16m8 (v3, vl); > + > + asm volatile("nop" ::: "memory"); > + size_t sum0 =3D __riscv_vmv_x_s_i16m8_i16 (vw0); > + size_t sum1 =3D __riscv_vmv_x_s_i16m8_i16 (vw1); > + size_t sum2 =3D __riscv_vmv_x_s_i16m8_i16 (vw2); > + size_t sum3 =3D __riscv_vmv_x_s_i16m8_i16 (vw3); > + > + sum +=3D sumation (sum0, sum1, sum2, sum3); > + } > + return sum; > +} > + > +/* { dg-final { scan-assembler-not {vmv1r} } } */ > +/* { dg-final { scan-assembler-not {vmv2r} } } */ > +/* { dg-final { scan-assembler-not {vmv4r} } } */ > +/* { dg-final { scan-assembler-not {vmv8r} } } */ > +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ > -- > 2.34.1 > > > > --00000000000013d5210616e340c3--