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Mon, 29 May 2023 19:04:22 -0700 (PDT) MIME-Version: 1.0 References: <20230529065321.200141-1-juzhe.zhong@rivai.ai> <4F3B176A452143D1+20230530083016597173312@rivai.ai> In-Reply-To: <4F3B176A452143D1+20230530083016597173312@rivai.ai> From: Kito Cheng Date: Tue, 30 May 2023 10:04:10 +0800 Message-ID: Subject: Re: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support To: "juzhe.zhong@rivai.ai" Cc: gcc-patches , "Kito.cheng" , palmer , palmer , jeffreyalaw , Robin Dapp Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Tue, May 30, 2023 at 8:30=E2=80=AFAM juzhe.zhong@rivai.ai wrote: > > Hi, this patch is same implementation as FMA which has been merged. > Ok for trunk? > > > > juzhe.zhong@rivai.ai > > From: juzhe.zhong > Date: 2023-05-29 14:53 > To: gcc-patches > CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe= -Zhong > Subject: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support > From: Juzhe-Zhong > > Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support. > > gcc/ChangeLog: > > * config/riscv/autovec.md (fnma4): New pattern. > (*fnma): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test. > * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test. > * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test. > > --- > gcc/config/riscv/autovec.md | 45 ++++++++ > .../riscv/rvv/autovec/ternop/ternop-4.c | 28 +++++ > .../riscv/rvv/autovec/ternop/ternop-5.c | 34 ++++++ > .../riscv/rvv/autovec/ternop/ternop-6.c | 33 ++++++ > .../riscv/rvv/autovec/ternop/ternop_run-4.c | 84 ++++++++++++++ > .../riscv/rvv/autovec/ternop/ternop_run-5.c | 104 ++++++++++++++++++ > .../riscv/rvv/autovec/ternop/ternop_run-6.c | 104 ++++++++++++++++++ > 7 files changed, 432 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/tern= op-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/tern= op-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/tern= op-6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/tern= op_run-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/tern= op_run-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/tern= op_run-6.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index eff3e484fb4..a1028d71467 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -606,3 +606,48 @@ > } > [(set_attr "type" "vimuladd") > (set_attr "mode" "")]) > + > +;; ---------------------------------------------------------------------= ---- > +;; ---- [INT] VNMSAC and VNMSUB > +;; ---------------------------------------------------------------------= ---- > +;; Includes: > +;; - vnmsac > +;; - vnmsub > +;; ---------------------------------------------------------------------= ---- > + > +(define_expand "fnma4" > + [(parallel > + [(set (match_operand:VI 0 "register_operand" "=3Dvr") > + (minus:VI > + (match_operand:VI 3 "register_operand" " vr") > + (mult:VI > + (match_operand:VI 1 "register_operand" " vr") > + (match_operand:VI 2 "register_operand" " vr")))) > + (clobber (match_scratch:SI 4))])] > + "TARGET_VECTOR" > + {}) > + > +(define_insn_and_split "*fnma" > + [(set (match_operand:VI 0 "register_operand" "=3Dvr, vr, ?&vr") > + (minus:VI > + (match_operand:VI 3 "register_operand" " vr, 0, vr") > + (mult:VI > + (match_operand:VI 1 "register_operand" " %0, vr, vr") > + (match_operand:VI 2 "register_operand" " vr, vr, vr")))) > + (clobber (match_scratch:SI 4 "=3Dr,r,r"))] > + "TARGET_VECTOR" > + "#" > + "&& reload_completed" > + [(const_int 0)] > + { > + PUT_MODE (operands[4], Pmode); > + riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > + if (which_alternative =3D=3D 2) > + emit_insn (gen_rtx_SET (operands[0], operands[3])); > + rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > + riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), > + riscv_vector::RVV_TERNOP, ops, operands[4]); > + DONE; > + } > + [(set_attr "type" "vimuladd") > + (set_attr "mode" "")]) > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c > new file mode 100644 > index 00000000000..22d11de89a1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define TEST_TYPE(TYPE) = \ > + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst, = \ > + TYPE *__restrict a, \ > + TYPE *__restrict b, int n) \ > + { = \ > + for (int i =3D 0; i < n; i++) = \ > + dst[i] +=3D -(a[i] * b[i]); = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int8_t) = \ > + TEST_TYPE (uint8_t) = \ > + TEST_TYPE (int16_t) = \ > + TEST_TYPE (uint16_t) = \ > + TEST_TYPE (int32_t) = \ > + TEST_TYPE (uint32_t) = \ > + TEST_TYPE (int64_t) = \ > + TEST_TYPE (uint64_t) > + > +TEST_ALL () > + > +/* { dg-final { scan-assembler-times {\tvnmsub\.vv} 8 } } */ > +/* { dg-final { scan-assembler-not {\tvmv} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c > new file mode 100644 > index 00000000000..6d5cf0a4da3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c > @@ -0,0 +1,34 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define TEST_TYPE(TYPE) = \ > + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, = \ > + TYPE *__restrict dest2, \ > + TYPE *__restrict dest3, \ > + TYPE *__restrict src1, \ > + TYPE *__restrict src2, int n) \ > + { = \ > + for (int i =3D 0; i < n; ++i) = \ > + { = \ > + dest1[i] +=3D -(src1[i] * src2[i]); = \ > + dest2[i] +=3D src1[i] * dest1[i]; = \ > + dest3[i] +=3D src2[i] * dest2[i]; = \ > + } = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int8_t) = \ > + TEST_TYPE (uint8_t) = \ > + TEST_TYPE (int16_t) = \ > + TEST_TYPE (uint16_t) = \ > + TEST_TYPE (int32_t) = \ > + TEST_TYPE (uint32_t) = \ > + TEST_TYPE (int64_t) = \ > + TEST_TYPE (uint64_t) > + > +TEST_ALL () > + > +/* { dg-final { scan-assembler-times {\tvnmsac\.vv} 8 } } */ > +/* { dg-final { scan-assembler-not {\tvmv} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c > new file mode 100644 > index 00000000000..a2186e67222 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define TEST_TYPE(TYPE) = \ > + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, = \ > + TYPE *__restrict dest2, \ > + TYPE *__restrict dest3, \ > + TYPE *__restrict src1, \ > + TYPE *__restrict src2, int n) \ > + { = \ > + for (int i =3D 0; i < n; ++i) = \ > + { = \ > + dest1[i] =3D -(src1[i] * src2[i]) + dest2[i]; = \ > + dest2[i] +=3D src1[i] * dest1[i]; = \ > + dest3[i] +=3D src2[i] * dest2[i]; = \ > + } = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int8_t) = \ > + TEST_TYPE (uint8_t) = \ > + TEST_TYPE (int16_t) = \ > + TEST_TYPE (uint16_t) = \ > + TEST_TYPE (int32_t) = \ > + TEST_TYPE (uint32_t) = \ > + TEST_TYPE (int64_t) = \ > + TEST_TYPE (uint64_t) > + > +TEST_ALL () > + > +/* { dg-final { scan-assembler-times {\tvmv} 8 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run= -4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c > new file mode 100644 > index 00000000000..379ab259816 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c > @@ -0,0 +1,84 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include "ternop-4.c" > + > +#define TEST_LOOP(TYPE, NUM) = \ > + { = \ > + TYPE array1_##NUM[NUM] =3D {}; = \ > + TYPE array2_##NUM[NUM] =3D {}; = \ > + TYPE array3_##NUM[NUM] =3D {}; = \ > + TYPE array4_##NUM[NUM] =3D {}; = \ > + for (int i =3D 0; i < NUM; ++i) = \ > + { = \ > + array1_##NUM[i] =3D (i & 1) + 5; = \ > + array2_##NUM[i] =3D i - NUM / 3; = \ > + array3_##NUM[i] =3D NUM - NUM / 3 - i; = \ > + array4_##NUM[i] =3D NUM - NUM / 3 - i; = \ > + asm volatile("" ::: "memory"); = \ > + } = \ > + ternop_##TYPE (array3_##NUM, array1_##NUM, array2_##NUM, NUM); = \ > + for (int i =3D 0; i < NUM; i++) = \ > + if (array3_##NUM[i] = \ > + !=3D (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array4_##NUM[i]))= \ > + __builtin_abort (); = \ > + } > + > +int __attribute__ ((optimize (0))) main () > +{ > + TEST_LOOP (int8_t, 7) > + TEST_LOOP (uint8_t, 7) > + TEST_LOOP (int16_t, 7) > + TEST_LOOP (uint16_t, 7) > + TEST_LOOP (int32_t, 7) > + TEST_LOOP (uint32_t, 7) > + TEST_LOOP (int64_t, 7) > + TEST_LOOP (uint64_t, 7) > + > + TEST_LOOP (int8_t, 16) > + TEST_LOOP (uint8_t, 16) > + TEST_LOOP (int16_t, 16) > + TEST_LOOP (uint16_t, 16) > + TEST_LOOP (int32_t, 16) > + TEST_LOOP (uint32_t, 16) > + TEST_LOOP (int64_t, 16) > + TEST_LOOP (uint64_t, 16) > + > + TEST_LOOP (int8_t, 77) > + TEST_LOOP (uint8_t, 77) > + TEST_LOOP (int16_t, 77) > + TEST_LOOP (uint16_t, 77) > + TEST_LOOP (int32_t, 77) > + TEST_LOOP (uint32_t, 77) > + TEST_LOOP (int64_t, 77) > + TEST_LOOP (uint64_t, 77) > + > + TEST_LOOP (int8_t, 128) > + TEST_LOOP (uint8_t, 128) > + TEST_LOOP (int16_t, 128) > + TEST_LOOP (uint16_t, 128) > + TEST_LOOP (int32_t, 128) > + TEST_LOOP (uint32_t, 128) > + TEST_LOOP (int64_t, 128) > + TEST_LOOP (uint64_t, 128) > + > + TEST_LOOP (int8_t, 15641) > + TEST_LOOP (uint8_t, 15641) > + TEST_LOOP (int16_t, 15641) > + TEST_LOOP (uint16_t, 15641) > + TEST_LOOP (int32_t, 15641) > + TEST_LOOP (uint32_t, 15641) > + TEST_LOOP (int64_t, 15641) > + TEST_LOOP (uint64_t, 15641) > + > + TEST_LOOP (int8_t, 795) > + TEST_LOOP (uint8_t, 795) > + TEST_LOOP (int16_t, 795) > + TEST_LOOP (uint16_t, 795) > + TEST_LOOP (int32_t, 795) > + TEST_LOOP (uint32_t, 795) > + TEST_LOOP (int64_t, 795) > + TEST_LOOP (uint64_t, 795) > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run= -5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c > new file mode 100644 > index 00000000000..f9bdf92cc2c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c > @@ -0,0 +1,104 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include "ternop-5.c" > + > +#define TEST_LOOP(TYPE, NUM) = \ > + { = \ > + TYPE array1_##NUM[NUM] =3D {}; = \ > + TYPE array2_##NUM[NUM] =3D {}; = \ > + TYPE array3_##NUM[NUM] =3D {}; = \ > + TYPE array4_##NUM[NUM] =3D {}; = \ > + TYPE array5_##NUM[NUM] =3D {}; = \ > + TYPE array6_##NUM[NUM] =3D {}; = \ > + TYPE array7_##NUM[NUM] =3D {}; = \ > + TYPE array8_##NUM[NUM] =3D {}; = \ > + for (int i =3D 0; i < NUM; ++i) = \ > + { = \ > + array1_##NUM[i] =3D (i & 1) + 5; = \ > + array2_##NUM[i] =3D i - NUM / 3; = \ > + array3_##NUM[i] =3D NUM - NUM / 3 - i; = \ > + array6_##NUM[i] =3D NUM - NUM / 3 - i; = \ > + array4_##NUM[i] =3D NUM - NUM / 2 + i; = \ > + array7_##NUM[i] =3D NUM - NUM / 2 + i; = \ > + array5_##NUM[i] =3D NUM + i * 7; = \ > + array8_##NUM[i] =3D NUM + i * 7; = \ > + asm volatile("" ::: "memory"); = \ > + } = \ > + ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NU= M, \ > + array2_##NUM, NUM); \ > + for (int i =3D 0; i < NUM; i++) = \ > + { = \ > + array6_##NUM[i] = \ > + =3D (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array6_##NUM[i]); = \ > + if (array3_##NUM[i] !=3D array6_##NUM[i]) = \ > + __builtin_abort (); = \ > + array7_##NUM[i] = \ > + =3D (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); = \ > + if (array4_##NUM[i] !=3D array7_##NUM[i]) = \ > + __builtin_abort (); = \ > + array8_##NUM[i] = \ > + =3D (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); = \ > + if (array5_##NUM[i] !=3D array8_##NUM[i]) = \ > + __builtin_abort (); = \ > + } = \ > + } > + > +int __attribute__ ((optimize (0))) main () > +{ > + TEST_LOOP (int8_t, 7) > + TEST_LOOP (uint8_t, 7) > + TEST_LOOP (int16_t, 7) > + TEST_LOOP (uint16_t, 7) > + TEST_LOOP (int32_t, 7) > + TEST_LOOP (uint32_t, 7) > + TEST_LOOP (int64_t, 7) > + TEST_LOOP (uint64_t, 7) > + > + TEST_LOOP (int8_t, 16) > + TEST_LOOP (uint8_t, 16) > + TEST_LOOP (int16_t, 16) > + TEST_LOOP (uint16_t, 16) > + TEST_LOOP (int32_t, 16) > + TEST_LOOP (uint32_t, 16) > + TEST_LOOP (int64_t, 16) > + TEST_LOOP (uint64_t, 16) > + > + TEST_LOOP (int8_t, 77) > + TEST_LOOP (uint8_t, 77) > + TEST_LOOP (int16_t, 77) > + TEST_LOOP (uint16_t, 77) > + TEST_LOOP (int32_t, 77) > + TEST_LOOP (uint32_t, 77) > + TEST_LOOP (int64_t, 77) > + TEST_LOOP (uint64_t, 77) > + > + TEST_LOOP (int8_t, 128) > + TEST_LOOP (uint8_t, 128) > + TEST_LOOP (int16_t, 128) > + TEST_LOOP (uint16_t, 128) > + TEST_LOOP (int32_t, 128) > + TEST_LOOP (uint32_t, 128) > + TEST_LOOP (int64_t, 128) > + TEST_LOOP (uint64_t, 128) > + > + TEST_LOOP (int8_t, 15641) > + TEST_LOOP (uint8_t, 15641) > + TEST_LOOP (int16_t, 15641) > + TEST_LOOP (uint16_t, 15641) > + TEST_LOOP (int32_t, 15641) > + TEST_LOOP (uint32_t, 15641) > + TEST_LOOP (int64_t, 15641) > + TEST_LOOP (uint64_t, 15641) > + > + TEST_LOOP (int8_t, 795) > + TEST_LOOP (uint8_t, 795) > + TEST_LOOP (int16_t, 795) > + TEST_LOOP (uint16_t, 795) > + TEST_LOOP (int32_t, 795) > + TEST_LOOP (uint32_t, 795) > + TEST_LOOP (int64_t, 795) > + TEST_LOOP (uint64_t, 795) > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run= -6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c > new file mode 100644 > index 00000000000..c000e331084 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c > @@ -0,0 +1,104 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include "ternop-6.c" > + > +#define TEST_LOOP(TYPE, NUM) = \ > + { = \ > + TYPE array1_##NUM[NUM] =3D {}; = \ > + TYPE array2_##NUM[NUM] =3D {}; = \ > + TYPE array3_##NUM[NUM] =3D {}; = \ > + TYPE array4_##NUM[NUM] =3D {}; = \ > + TYPE array5_##NUM[NUM] =3D {}; = \ > + TYPE array6_##NUM[NUM] =3D {}; = \ > + TYPE array7_##NUM[NUM] =3D {}; = \ > + TYPE array8_##NUM[NUM] =3D {}; = \ > + for (int i =3D 0; i < NUM; ++i) = \ > + { = \ > + array1_##NUM[i] =3D (i & 1) + 5; = \ > + array2_##NUM[i] =3D i - NUM / 3; = \ > + array3_##NUM[i] =3D NUM - NUM / 3 - i; = \ > + array6_##NUM[i] =3D NUM - NUM / 3 - i; = \ > + array4_##NUM[i] =3D NUM - NUM / 2 + i; = \ > + array7_##NUM[i] =3D NUM - NUM / 2 + i; = \ > + array5_##NUM[i] =3D NUM + i * 7; = \ > + array8_##NUM[i] =3D NUM + i * 7; = \ > + asm volatile("" ::: "memory"); = \ > + } = \ > + ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NU= M, \ > + array2_##NUM, NUM); \ > + for (int i =3D 0; i < NUM; i++) = \ > + { = \ > + array6_##NUM[i] = \ > + =3D (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array7_##NUM[i]); = \ > + if (array3_##NUM[i] !=3D array6_##NUM[i]) = \ > + __builtin_abort (); = \ > + array7_##NUM[i] = \ > + =3D (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); = \ > + if (array4_##NUM[i] !=3D array7_##NUM[i]) = \ > + __builtin_abort (); = \ > + array8_##NUM[i] = \ > + =3D (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); = \ > + if (array5_##NUM[i] !=3D array8_##NUM[i]) = \ > + __builtin_abort (); = \ > + } = \ > + } > + > +int __attribute__ ((optimize (0))) main () > +{ > + TEST_LOOP (int8_t, 7) > + TEST_LOOP (uint8_t, 7) > + TEST_LOOP (int16_t, 7) > + TEST_LOOP (uint16_t, 7) > + TEST_LOOP (int32_t, 7) > + TEST_LOOP (uint32_t, 7) > + TEST_LOOP (int64_t, 7) > + TEST_LOOP (uint64_t, 7) > + > + TEST_LOOP (int8_t, 16) > + TEST_LOOP (uint8_t, 16) > + TEST_LOOP (int16_t, 16) > + TEST_LOOP (uint16_t, 16) > + TEST_LOOP (int32_t, 16) > + TEST_LOOP (uint32_t, 16) > + TEST_LOOP (int64_t, 16) > + TEST_LOOP (uint64_t, 16) > + > + TEST_LOOP (int8_t, 77) > + TEST_LOOP (uint8_t, 77) > + TEST_LOOP (int16_t, 77) > + TEST_LOOP (uint16_t, 77) > + TEST_LOOP (int32_t, 77) > + TEST_LOOP (uint32_t, 77) > + TEST_LOOP (int64_t, 77) > + TEST_LOOP (uint64_t, 77) > + > + TEST_LOOP (int8_t, 128) > + TEST_LOOP (uint8_t, 128) > + TEST_LOOP (int16_t, 128) > + TEST_LOOP (uint16_t, 128) > + TEST_LOOP (int32_t, 128) > + TEST_LOOP (uint32_t, 128) > + TEST_LOOP (int64_t, 128) > + TEST_LOOP (uint64_t, 128) > + > + TEST_LOOP (int8_t, 15641) > + TEST_LOOP (uint8_t, 15641) > + TEST_LOOP (int16_t, 15641) > + TEST_LOOP (uint16_t, 15641) > + TEST_LOOP (int32_t, 15641) > + TEST_LOOP (uint32_t, 15641) > + TEST_LOOP (int64_t, 15641) > + TEST_LOOP (uint64_t, 15641) > + > + TEST_LOOP (int8_t, 795) > + TEST_LOOP (uint8_t, 795) > + TEST_LOOP (int16_t, 795) > + TEST_LOOP (uint16_t, 795) > + TEST_LOOP (int32_t, 795) > + TEST_LOOP (uint32_t, 795) > + TEST_LOOP (int64_t, 795) > + TEST_LOOP (uint64_t, 795) > + > + return 0; > +} > -- > 2.36.3 >