From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe35.google.com (mail-vs1-xe35.google.com [IPv6:2607:f8b0:4864:20::e35]) by sourceware.org (Postfix) with ESMTPS id CB8DB3858409 for ; Fri, 21 Jul 2023 03:49:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB8DB3858409 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe35.google.com with SMTP id ada2fe7eead31-444c42f608aso619407137.1 for ; Thu, 20 Jul 2023 20:49:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689911372; x=1690516172; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=AnfAh0L0mvZei3MDg+QvDEGil1mEe/eq6r33nyAMpDA=; b=r27xye8GZ8qRxHxluvsX2zCAzeG+ECFkVmQ0kCEoGCklvinkA7qeKOXwQ25TrXtlQq BZm7216ioNjUAS0RfAttkDLR+804VTq8W7v7jvPxqfqujkXlpOt5rlqwfSVL+nQn+J6K mNFNstqUgLzgnq4CxgDJ7l2nQ/lUgTPvYCdqT1RHFi/RwNFYyfUVTGX6E/nJgv7GsykX wVKQ1SdztE1IdPk86HbgGJhnDyXBmKxHQ1BvNezUQQ/Eq9gYos4Mt4475xmz0MY46hDz IUCFClZzBDPbWa6fZXGp0lgJk/ihg27217XH+H+IJARyfjb9J4cWe1n+wdxH8r7yoO1w h8qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689911372; x=1690516172; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AnfAh0L0mvZei3MDg+QvDEGil1mEe/eq6r33nyAMpDA=; b=RCe8A3qteXmD6TpPmYrFd72IPIdI+kdzJxEmdI5xphUOT6hc1gOLY4x5mxk5e4rW+b 4Xxh3lu8bvM5J7q+/v311F3mVqcplqX/eE3j/CYlz2ewIhDE7ucTeuJm++uYVdGIULIV PLHeJGYuppD/jFfhiemni1cuiApDkvpWO8hMqAJHkJJxUw1yeU6PUQmzOq7oML0wJ4zU dBzES2n9L1GvcaXOYBKEgaw/Q0rLIlmIxo5SpzkgRC3lzDXkshXBzD/Fki2Dx4r0Opc+ ClHS3G6PqeOGg8P21peryfB0otGP6ikFHsor+TnfzWoWQ03NGlDnENTltb42nK8K5Q7k K4pg== X-Gm-Message-State: ABy/qLZmaGdCEWjWM2bUHtVmh477Ml1uPDQjFzs8auPE28SU0zrWzgXS b39INH4flZhr0fCIy2fGEHydBpQ2KF2mk/J1CtE= X-Google-Smtp-Source: APBJJlEnfQSW9jWMd3r/ow02IpMa6B61jmxkkesYLCDzNsv4QGHtQplARCp4x/ON+ds1BxWtyYWe+RUNI482SsIs8RI= X-Received: by 2002:a05:6102:3a4e:b0:443:841d:b02d with SMTP id c14-20020a0561023a4e00b00443841db02dmr400292vsu.17.1689911372126; Thu, 20 Jul 2023 20:49:32 -0700 (PDT) MIME-Version: 1.0 References: <20230602070726.3807539-1-yanzhang.wang@intel.com> <20230718074958.2806939-1-yanzhang.wang@intel.com> In-Reply-To: <20230718074958.2806939-1-yanzhang.wang@intel.com> From: Kito Cheng Date: Fri, 21 Jul 2023 11:49:20 +0800 Message-ID: Subject: Re: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-pointer support. To: yanzhang.wang@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@sifive.com, jeffreyalaw@gmail.com, pan2.li@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, I think long jump is another issue and making ra become a fixed register will escalate to an ABI issue, so that should not be a blocker for this patch. On Tue, Jul 18, 2023 at 4:10=E2=80=AFPM yanzhang.wang--- via Gcc-patches wrote: > > From: Yanzhang Wang > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf > when enabling -mno-omit-leaf-frame-pointer > (riscv_option_override): Override omit-frame-pointer. > (riscv_frame_pointer_required): Save s0 for non-leaf function > (TARGET_FRAME_POINTER_REQUIRED): Override defination > * config/riscv/riscv.opt: Add option support. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/omit-frame-pointer-1.c: New test. > * gcc.target/riscv/omit-frame-pointer-2.c: New test. > * gcc.target/riscv/omit-frame-pointer-3.c: New test. > * gcc.target/riscv/omit-frame-pointer-4.c: New test. > * gcc.target/riscv/omit-frame-pointer-test.c: New test. > > Signed-off-by: Yanzhang Wang > --- > gcc/config/riscv/riscv.cc | 34 ++++++++++++++++++- > gcc/config/riscv/riscv.opt | 4 +++ > .../gcc.target/riscv/omit-frame-pointer-1.c | 7 ++++ > .../gcc.target/riscv/omit-frame-pointer-2.c | 7 ++++ > .../gcc.target/riscv/omit-frame-pointer-3.c | 7 ++++ > .../gcc.target/riscv/omit-frame-pointer-4.c | 7 ++++ > .../riscv/omit-frame-pointer-test.c | 13 +++++++ > 7 files changed, 78 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-tes= t.c > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 706c18416db..caae6168c29 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -379,6 +379,10 @@ static const struct riscv_tune_info riscv_tune_info_= table[] =3D { > #include "riscv-cores.def" > }; > > +/* Global variable to distinguish whether we should save and restore s0/= fp for > + function. */ > +static bool riscv_save_frame_pointer; > + > void riscv_frame_info::reset(void) > { > total_size =3D 0; > @@ -4948,7 +4952,11 @@ riscv_save_reg_p (unsigned int regno) > if (regno =3D=3D HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) > return true; > > - if (regno =3D=3D RETURN_ADDR_REGNUM && crtl->calls_eh_return) > + /* Need not to use ra for leaf when frame pointer is turned off by opt= ion > + whatever the omit-leaf-frame's value. */ > + bool keep_leaf_ra =3D frame_pointer_needed && crtl->is_leaf > + && !TARGET_OMIT_LEAF_FRAME_POINTER; > + if (regno =3D=3D RETURN_ADDR_REGNUM && (crtl->calls_eh_return || keep_= leaf_ra)) > return true; > > /* If this is an interrupt handler, then must save extra registers. *= / > @@ -6577,6 +6585,21 @@ riscv_option_override (void) > if (flag_pic) > riscv_cmodel =3D CM_PIC; > > + /* We need to save the fp with ra for non-leaf functions with no fp an= d ra > + for leaf functions while no-omit-frame-pointer with > + omit-leaf-frame-pointer. The x_flag_omit_frame_pointer has the fir= st > + priority to determine whether the frame pointer is needed. If we d= o not > + override it, the fp and ra will be stored for leaf functions, which= is not > + our wanted. */ > + riscv_save_frame_pointer =3D false; > + if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags)) > + { > + if (!global_options.x_flag_omit_frame_pointer) > + riscv_save_frame_pointer =3D true; > + > + global_options.x_flag_omit_frame_pointer =3D 1; > + } > + > /* We get better code with explicit relocs for CM_MEDLOW, but > worse code for the others (for now). Pick the best default. */ > if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) =3D=3D 0) > @@ -7857,6 +7880,12 @@ riscv_preferred_else_value (unsigned, tree, unsign= ed int nops, tree *ops) > return nops =3D=3D 3 ? ops[2] : ops[0]; > } > > +static bool > +riscv_frame_pointer_required (void) > +{ > + return riscv_save_frame_pointer && !crtl->is_leaf; > +} > + > /* Initialize the GCC target structure. */ > #undef TARGET_ASM_ALIGNED_HI_OP > #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" > @@ -8161,6 +8190,9 @@ riscv_preferred_else_value (unsigned, tree, unsigne= d int nops, tree *ops) > #undef TARGET_PREFERRED_ELSE_VALUE > #define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value > > +#undef TARGET_FRAME_POINTER_REQUIRED > +#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required > + > struct gcc_target targetm =3D TARGET_INITIALIZER; > > #include "gt-riscv.h" > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index dd062f1c8bd..4dfd8f78ad5 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -138,6 +138,10 @@ Enable the CSR checking for the ISA-dependent CRS an= d the read-only CSR. > The ISA-dependent CSR are only valid when the specific ISA is set. The > read-only CSR can not be written by the CSR instructions. > > +momit-leaf-frame-pointer > +Target Mask(OMIT_LEAF_FRAME_POINTER) Save > +Omit the frame pointer in leaf functions. > + > Mask(64BIT) > > Mask(MUL) > diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c b/gcc/= testsuite/gcc.target/riscv/omit-frame-pointer-1.c > new file mode 100644 > index 00000000000..c96123ea702 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fno-omit-frame-pointe= r -mno-omit-leaf-frame-pointer -fno-inline" } */ > + > +#include "omit-frame-pointer-test.c" > + > +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 2 } } */ > +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 2 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c b/gcc/= testsuite/gcc.target/riscv/omit-frame-pointer-2.c > new file mode 100644 > index 00000000000..067148c6a58 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fno-omit-frame-pointe= r -momit-leaf-frame-pointer -fno-inline" } */ > + > +#include "omit-frame-pointer-test.c" > + > +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ > +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c b/gcc/= testsuite/gcc.target/riscv/omit-frame-pointer-3.c > new file mode 100644 > index 00000000000..b4d7d6f4f0d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fomit-frame-pointer -= mno-omit-leaf-frame-pointer -fno-inline" } */ > + > +#include "omit-frame-pointer-test.c" > + > +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ > +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */ > diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c b/gcc/= testsuite/gcc.target/riscv/omit-frame-pointer-4.c > new file mode 100644 > index 00000000000..5a5b540ef4e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fomit-frame-pointer -= momit-leaf-frame-pointer -fno-inline" } */ > + > +#include "omit-frame-pointer-test.c" > + > +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ > +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */ > diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c b/g= cc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c > new file mode 100644 > index 00000000000..cf19f001e29 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c > @@ -0,0 +1,13 @@ > +int inc(int n) > +{ > + return n + 1; > +} > + > + > +int bar(void) > +{ > + int n =3D 100; > + n =3D inc(n); > + n =3D inc(n) + 100; > + return n; > +} > -- > 2.40.1 >