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Sun, 21 Jan 2024 19:00:14 -0800 (PST) MIME-Version: 1.0 References: <20240122024905.1543475-1-juzhe.zhong@rivai.ai> In-Reply-To: <20240122024905.1543475-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Mon, 22 Jan 2024 11:00:02 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM :) On Mon, Jan 22, 2024 at 10:49=E2=80=AFAM Juzhe-Zhong = wrote: > > vfirst/vmsbf/vmsif/vmsof instructions are supposed to demand ratio instea= d of demanding sew_lmul. > But my previous typo makes VSETVL PASS miss honor the risc-v v spec. > > Consider this following simple case: > > int foo4 (void * in, void * out) > { > vint32m1_t v =3D __riscv_vle32_v_i32m1 (in, 4); > v =3D __riscv_vadd_vv_i32m1 (v, v, 4); > vbool32_t mask =3D __riscv_vreinterpret_v_i32m1_b32(v); > mask =3D __riscv_vmsof_m_b32(mask, 4); > return __riscv_vfirst_m_b32(mask, 4); > } > > Before this patch: > > foo4: > vsetivli zero,4,e32,m1,ta,ma > vle32.v v1,0(a0) > vadd.vv v1,v1,v1 > vsetvli zero,zero,e8,mf4,ta,ma ----> redundant. > vmsof.m v2,v1 > vfirst.m a0,v2 > ret > > After this patch: > > foo4: > vsetivli zero,4,e32,m1,ta,ma > vle32.v v1,0(a0) > vadd.vv v1,v1,v1 > vmsof.m v2,v1 > vfirst.m a0,v2 > ret > > Confirm RVV spec and Clang, this patch makes VSETVL PASS match the correc= t behavior. > > Tested on both RV32/RV64, no regression. > > gcc/ChangeLog: > > * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes= . > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/attribute-1.c: New test. > > --- > gcc/config/riscv/vector.md | 2 +- > .../gcc.target/riscv/rvv/vsetvl/attribute-1.c | 47 +++++++++++++++++++ > 2 files changed, 48 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1= .c > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index cfc54ae5eac..307d9a8c952 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -433,7 +433,7 @@ > vialu,vshift,vicmp,vimul,vidiv,vsalu,\ > vext,viwalu,viwmul,vicalu,vnshift,\ > vimuladd,vimerge,vaalu,vsmul,vsshift,\ > - vnclip,viminmax,viwmuladd,vmffs,vmsfs,\ > + vnclip,viminmax,viwmuladd,\ > vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\ > vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\ > vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c b/gc= c/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c > new file mode 100644 > index 00000000000..28dcf986bac > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c > @@ -0,0 +1,47 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ > + > +#include "riscv_vector.h" > + > +int > +foo (void *in, void *out) > +{ > + vint32m1_t v =3D __riscv_vle32_v_i32m1 (in, 4); > + v =3D __riscv_vadd_vv_i32m1 (v, v, 4); > + vbool32_t mask =3D __riscv_vreinterpret_v_i32m1_b32 (v); > + return __riscv_vfirst_m_b32 (mask, 4); > +} > + > +int > +foo2 (void *in, void *out) > +{ > + vint32m1_t v =3D __riscv_vle32_v_i32m1 (in, 4); > + v =3D __riscv_vadd_vv_i32m1 (v, v, 4); > + vbool32_t mask =3D __riscv_vreinterpret_v_i32m1_b32 (v); > + mask =3D __riscv_vmsbf_m_b32 (mask, 4); > + return __riscv_vfirst_m_b32 (mask, 4); > +} > + > +int > +foo3 (void *in, void *out) > +{ > + vint32m1_t v =3D __riscv_vle32_v_i32m1 (in, 4); > + v =3D __riscv_vadd_vv_i32m1 (v, v, 4); > + vbool32_t mask =3D __riscv_vreinterpret_v_i32m1_b32 (v); > + mask =3D __riscv_vmsif_m_b32 (mask, 4); > + return __riscv_vfirst_m_b32 (mask, 4); > +} > + > +int > +foo4 (void *in, void *out) > +{ > + vint32m1_t v =3D __riscv_vle32_v_i32m1 (in, 4); > + v =3D __riscv_vadd_vv_i32m1 (v, v, 4); > + vbool32_t mask =3D __riscv_vreinterpret_v_i32m1_b32 (v); > + mask =3D __riscv_vmsof_m_b32 (mask, 4); > + return __riscv_vfirst_m_b32 (mask, 4); > +} > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,= \s*t[au],\s*m[au]} 4 } } */ > +/* { dg-final { scan-assembler-times {vsetivli} 4 } } */ > +/* { dg-final { scan-assembler-not {vsetvli} } } */ > -- > 2.36.3 >