From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb34.google.com (mail-yb1-xb34.google.com [IPv6:2607:f8b0:4864:20::b34]) by sourceware.org (Postfix) with ESMTPS id 0CA753858C50 for ; Fri, 21 Apr 2023 13:01:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0CA753858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb34.google.com with SMTP id 3f1490d57ef6-b8f549d36e8so2764853276.3 for ; Fri, 21 Apr 2023 06:01:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682082103; x=1684674103; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=4FzlEtONwoaq/tdPlPTQ3zpfBXwS2JbiubcnvhjB3Cg=; b=chHy4CvDkjQuRzFhILvm3uNwSwiZF0X7o4CSBeG4e/25fmk6DRiOyZeBtAaBNtNG/q qt7pFt3D//O3l3yZE2FKOiZwAy5oUFhCy3jC2hceq9xA8qBQdtxU2mE/KK/l7t5J2+2p tkZ8w7vwsk4o93UgqiUq3hUpEgjTanKAf3NKBMaLNfC20MuYqKzkGKQNCZoZ9jZNmFT6 q7a5PZCAlpM2Ay6TsHJoCxeJ1cSfYZrmGQDS65KbrUDwLWQtsBRYcmneWOHlWYpOqVKO F1zK24+PeQnp+/cvCdO7PFx6ATf0ReMoqMNbbV6aj/7KVeikrZUhXjyD+i5EGIRZ9UH5 La3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682082103; x=1684674103; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4FzlEtONwoaq/tdPlPTQ3zpfBXwS2JbiubcnvhjB3Cg=; b=UEX8hOq+/Y1eaiE/s6updGs3T2Jfj8V/wyRBqODJ7t8lwtmmXR3knA4I2ITNnM3cDk K9mWqvcbcrJvy5zi+hhna+jizSVlezqbavPUdJxij1jV21Vd4WbnrPXnIon9OWXxw1eZ 1XaTaFJBSRMa3yRNmBPZsTJFGbBTRgbcgzkQB6EwPmUq4q0uugrzgoion0pVQHH/6IU1 s73b0WELJBG65WqERw3985UV6oEvvNZsDdy2Y/bmhjDCD4AltKTSdfj2+6Au9OUljXcV wT87wL4d6hbEt0zfl1ySWp8Knql5tt4xg0WARwlOmaZYeaAk0DJDp0IG/yQCtCX9w9Ms b1Nw== X-Gm-Message-State: AAQBX9d3tzD+uGGUPmDMxXs0E7HE95ZB+RZdutVIHlSxMCAw85nlyoW1 MetFg4AyZw8p5lbBckaw+jWj5UAI/hK+Xu/WRQAs0huTudtYhA== X-Google-Smtp-Source: AKy350Ytqwm4BOCZCL0lapHEdX2Ur2/AHGbWeH2FzaCVV4wPUI61MPRxnKDwucxKkQhJ4FeazvURDBGGPnPmAx5UlWI= X-Received: by 2002:a05:7500:c41:b0:102:cc1f:c08 with SMTP id fz1-20020a0575000c4100b00102cc1f0c08mr242374gab.37.1682082102818; Fri, 21 Apr 2023 06:01:42 -0700 (PDT) MIME-Version: 1.0 References: <20230419032117.930737-1-pan2.li@intel.com> <2908B8F5933F9196+20230419174105693011142@rivai.ai> In-Reply-To: From: Kito Cheng Date: Fri, 21 Apr 2023 21:01:31 +0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization To: "Li, Pan2" Cc: "juzhe.zhong@rivai.ai" , gcc-patches , "Kito.cheng" , "Wang, Yanzhang" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Pan: One idea come to my mind, maybe we should add a new define_insn_and_split pattern instead of change @pred_mov On Fri, Apr 21, 2023 at 7:17=E2=80=AFPM Li, Pan2 via Gcc-patches wrote: > > Thanks kito, will try to reproduce this issue and keep you posted. > > Pan > > -----Original Message----- > From: Kito Cheng > Sent: Friday, April 21, 2023 6:17 PM > To: Li, Pan2 > Cc: juzhe.zhong@rivai.ai; gcc-patches ; Kito.che= ng ; Wang, Yanzhang > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut opt= imization > > I got a bunch of new fails including ICE for gcc testsuite, and some case= s are hanging there, could you take a look? > > $ riscv64-unknown-linux-gnu-gcc > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=3Drv32gcv > -mabi=3Dilp32 > during RTL pass: expand > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/tes= tsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c: > In function 'f': > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/tes= tsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13: > internal compiler error: in maybe_gen_insn, at optabs.cc:8102 > 8 | vbool64_t mask =3D *(vbool64_t*) (in + 1000000); > | ^~~~ > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*) > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102 > > > On Fri, Apr 21, 2023 at 5:47=E2=80=AFPM Li, Pan2 via Gcc-patches wrote: > > > > Kindly ping for the PATCH v2. Just FYI there will be some underlying in= vestigation based on this PATCH like VMSEQ. > > > > Pan > > > > -----Original Message----- > > From: Li, Pan2 > > Sent: Wednesday, April 19, 2023 7:27 PM > > To: 'Kito Cheng' ; 'juzhe.zhong@rivai.ai' > > > > Cc: 'gcc-patches' ; 'Kito.cheng' > > ; Wang, Yanzhang > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut > > optimization > > > > Update the Patch v2 for more detail information for clarification. Plea= se help to review continuously. > > > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html > > > > Pan > > > > -----Original Message----- > > From: Li, Pan2 > > Sent: Wednesday, April 19, 2023 6:33 PM > > To: Kito Cheng ; juzhe.zhong@rivai.ai > > Cc: gcc-patches ; Kito.cheng > > ; Wang, Yanzhang > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut > > optimization > > > > Sure thing. > > > > For Changlog, I consider it was generated automatically in previous. LO= L. > > > > Pan > > > > -----Original Message----- > > From: Kito Cheng > > Sent: Wednesday, April 19, 2023 5:46 PM > > To: juzhe.zhong@rivai.ai > > Cc: Li, Pan2 ; gcc-patches > > ; Kito.cheng ; Wang, > > Yanzhang > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut > > optimization > > > > HI JuZhe: > > > > Thanks for explaining! > > > > > > Hi Pan: > > > > I think that would be helpful if JuZhe's explaining that could be writt= en into the commit log. > > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv-v.cc (emit_pred_op): > > > * config/riscv/riscv-vector-builtins-bases.cc: > > > * config/riscv/vector.md: > > > > And don't forgot write some thing in ChangeLog...:P