From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id 3021E3858C36 for ; Wed, 28 Feb 2024 14:55:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3021E3858C36 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3021E3858C36 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::52b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709132124; cv=none; b=tmFo711jChL5S7PSl9zXlwT4PVpJCHKbHDhVdrSqW/Q62RqJH85QNz3shtJ+zlfUQdCk8ayH2G191FUly5X/SqrS4nh3l+g0jOti/rWfTGza5/mHElNl9EX5HUEC2lZiDhZ8rgytAFs7Tje+9LgajT32BxiM0L01ow1PN2UoXZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709132124; c=relaxed/simple; bh=wG+suvBnGM9rDodVpVyqhamXTcHNatL5KH1AmQayBxg=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=LXjqY4/YOZ/5z+YQNZUR+Euw2DlXC4gVUK+LlUjltD29BBls7/sNWmElwHY9+swo9JZhC0NBi8dcElhLSIQn9YLaeK4cX2AMFTlw67bCXjHhZAaH444vxjZdt2IhBZdu+EL/yi0bpb1hkn3YW8fEfo6Z6ZRL4csXM4wYP3aoFtU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-564372fb762so7806465a12.0 for ; Wed, 28 Feb 2024 06:55:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709132120; x=1709736920; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=K8gXDLvBcEsCD6LH+WiPK9SXYnTCWFTmi01Sacsb30A=; b=UzslM7o+gFA9uglDyJEmzzOgVKzn8zOM2Pn4pLyaevzvLAxROjZEF4e1Nj3pl/v8sr T9gUqUYzwdS75E+SNZJwtoF5XSblw4qUmP3PsdoiqELuU/aY5jClcmFOt1CIGoGeDuji 1/T+GLWRaAhxSUDGjdzzoPhnh2AzIEz8NwU7Kem9ecEJl4RZemkvd9erpuwRnEK2Oc3f JeBtWg+Gr2h61IkxmrFGy8FQ0qeU082by5hcYXtw7E7e7LBp7+N5dyskstGw7mS950F3 Jf184U0ph6NYP+wA/Z/Glv/IvmKLAF/Nro02kT6xcE9SdNf31Jp+sxSU5fwhVSQI6OYy GUYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709132120; x=1709736920; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=K8gXDLvBcEsCD6LH+WiPK9SXYnTCWFTmi01Sacsb30A=; b=hspjzdKbaEqVcMB7FvIKxyfIDn1QWW2oX4HGq7DT0u3+CstpwDMiWJZMHcyXCs1d9/ wPhE6sDr9mRMWCSDIGDoLRGyaTbYd+WwEp5GWv33qY8Y+36ujTyXdoH/L1jBWLrYlSqZ GDgDkIxOL94nj7rtu3IIp5cw3KPTYhdKK0yqEG0Nh+GG4kkx0IwEUI2WOich5uMeot0/ BOwHKlmcvxq2LNF3g87FiWgde0AujLAdZeGU8V32jlKQ4ZzeExYzfzsJvMm3DiYy9LfV O8k4P+pkq0+mEZsaG2P+l5qaxrscxg9bM60RC5v+nDKR9QHZUMGvWV1fpxmYmBkhMRex ymTw== X-Forwarded-Encrypted: i=1; AJvYcCWFxkYc3kdcNcNzqN9AT3zl/QPzje6xIUwzSpUPDtmJbv4TuhpQEMCpw/J8qJa4+a4w0KhvQN63yhXw1Ia2LvGCuMRVe+mD7w== X-Gm-Message-State: AOJu0YyXwfepa0PbjbjoLEO30juCXDuaVkLUiUsXOlWmkpp8Xu8xXWbB 2czN5qYcmGBUG/di9o2n3a93TE7i2KpLrL/jirkH33HdgtNGeOzN1pQLeJZkfMJcjvnhgK4Kfwp ICfGIsSiw0C6/1Qz9wibTlN+212s= X-Google-Smtp-Source: AGHT+IHMNeBYkT2GgDik/5+IQKVy8R337jTlN/EX0xPVW93K130R9bKLz8Bop13foGqqgPcF2AF24wO1y886HoWuWpA= X-Received: by 2002:a05:6402:14d4:b0:565:dce3:66fd with SMTP id f20-20020a05640214d400b00565dce366fdmr7057812edx.23.1709132119414; Wed, 28 Feb 2024 06:55:19 -0800 (PST) MIME-Version: 1.0 References: <20240223080558.2644800-1-pan2.li@intel.com> <20240228103532.2079576-1-pan2.li@intel.com> <1AA40984DD2A43FA+202402282158578616418@rivai.ai> In-Reply-To: <1AA40984DD2A43FA+202402282158578616418@rivai.ai> From: Kito Cheng Date: Wed, 28 Feb 2024 22:55:07 +0800 Message-ID: Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: "pan2.li" , gcc-patches , "yanzhang.wang" , "rdapp.gcc" , Jeff Law Content-Type: multipart/alternative; boundary="000000000000da1ee90612725402" X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000da1ee90612725402 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hmm, maybe only keep --param=3Driscv-autovec-preference=3Dnone and remove o= ther two if we think that might still useful? But anyway I have no strong opinion to keep that, I mean I am ok to remove whole --param=3Driscv-autovec-preference. =E9=92=9F=E5=B1=85=E5=93=B2 =E6=96=BC 2024=E5=B9=B42= =E6=9C=8828=E6=97=A5 =E9=80=B1=E4=B8=89 21:59 =E5=AF=AB=E9=81=93=EF=BC=9A > I think it makes more sense to remove --param=3Driscv-autovec-preference = and > add -mrvv-vector-bits.... > > ------------------------------ > juzhe.zhong@rivai.ai > > > *From:* Kito Cheng > *Date:* 2024-02-28 20:56 > *To:* pan2.li > *CC:* gcc-patches ; juzhe.zhong > ; yanzhang.wang ; rdapp.gcc > ; jeffreyalaw > *Subject:* Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits > for RVV > Take one more look, I think this option should work and integrate with > --param=3Driscv-autovec-preference=3D since they have similar jobs but > slightly different. > > We have 3 value for --param=3Driscv-autovec-preference=3D: none, scalable > and fixed-vlmax > > -mrvv-vector-bits=3Dscalable is work like > --param=3Driscv-autovec-preference=3Dscalable and > -mrvv-vector-bits=3Dzvl is work like > --param=3Driscv-autovec-preference=3Dfixed-vlmax. > > So I think...we need to do some conflict check, like: > > -mrvv-vector-bits=3Dzvl can't work with > --param=3Driscv-autovec-preference=3Dscalable > -mrvv-vector-bits=3Dscalable can't work with > --param=3Driscv-autovec-preference=3Dfixed-vlmax > > but it may not just alias since there is some useful combinations like: > > -mrvv-vector-bits=3Dzvl with --param=3Driscv-autovec-preference=3Dnone: > NO auto vectorization but intrinsic code still could benefit from the > -mrvv-vector-bits=3Dzvl option. > > -mrvv-vector-bits=3Dscalable with --param=3Driscv-autovec-preference=3Dno= ne > Should still work for VLS code gen, but just disable auto > vectorization per the option semantic. > > However here is something we need some fix, since > --param=3Driscv-autovec-preference=3Dnone still disable VLS code gen for > now, you can see some example here: > https://godbolt.org/z/fMTr3eW7K > > But I think it's really the right behavior here, this part might need > to be fixed in vls_mode_valid_p and some other places. > > > Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and > RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX > also checked with RVV_VECTOR_BITS_ZVL. > > > > > -/* Return the VLEN value associated with -march. > > +static int > > +riscv_convert_vector_bits (int min_vlen) > > Not sure if we really need this function, it seems it always returns > min_vlen? > > > +{ > > + int rvv_bits =3D 0; > > + > > + switch (rvv_vector_bits) > > + { > > + case RVV_VECTOR_BITS_ZVL: > > + case RVV_VECTOR_BITS_SCALABLE: > > + rvv_bits =3D min_vlen; > > + break; > > + default: > > + gcc_unreachable (); > > + } > > + > > + return rvv_bits; > > +} > > + > > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. > > > --000000000000da1ee90612725402--