From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id 6CC93382BD13 for ; Tue, 7 Jun 2022 10:26:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6CC93382BD13 Received: by mail-ej1-x62d.google.com with SMTP id y19so34238477ejq.6 for ; Tue, 07 Jun 2022 03:26:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mB/TGKNu79eVICDXH11JQiBetWJd/v0BBEHQABE0+RQ=; b=V4Jbu49NiL4Mg83uyW2ykgkqG9Jz4ZF/jx+whtEzYFV8ovIdnPGNsl+S815/bOGTV0 uo4fcAz7HCQ4hQUDqLSLxSiakdNR2suwVNij08xU4T4pywsjuFi+dlXq6um7nzSZil+0 WBtuMPGG+ruciyxGPMzjZprBTCXGcV8vkePJe8J/aPY1PDekf1OmhLlBvUDjQj8eaqlc NnkT0JBDVrl6rWXZeOW74FdRQz+wF1XdHUE+rH2E9D9V/RMBiBKEicTAtrN7RDn8/M8X X/IFbHbftUd6Tb4/Hv04Hs4d9s6lyW3AaS4J9WUlqOmc2iJe1U1WDBpQvc7gv0vTVb+m bauA== X-Gm-Message-State: AOAM533yfVMGsjqwwZ4hzvKtDPc9Pksr77WKE936LFGzv2WJIglfJigY 8TUp0Fm6UP31o7dbezsI71AdFsncTo1XhEDtiok= X-Google-Smtp-Source: ABdhPJwODq6zktJ25JLt5SHOqfAOWK/rTJ9eLwOC2D4dVCkT3CjiyJPeGLVEp6Tujgd19pyfwRsQD64lkP0q+La8UUs= X-Received: by 2002:a17:907:6088:b0:6ff:16bc:98da with SMTP id ht8-20020a170907608800b006ff16bc98damr25036003ejc.441.1654597564193; Tue, 07 Jun 2022 03:26:04 -0700 (PDT) MIME-Version: 1.0 References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> <20220524214703.4022737-2-philipp.tomsich@vrull.eu> In-Reply-To: <20220524214703.4022737-2-philipp.tomsich@vrull.eu> From: Kito Cheng Date: Tue, 7 Jun 2022 18:25:51 +0800 Message-ID: Subject: Re: [PATCH v1 1/3] RISC-V: add consecutive_bits_operand predicate To: Philipp Tomsich Cc: GCC Patches , Andrew Waterman , Vineet Gupta Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Jun 2022 10:26:06 -0000 LGTM On Wed, May 25, 2022 at 5:48 AM Philipp Tomsich wrote: > > Provide an easy way to constrain for constants that are a a single, > consecutive run of ones. > > gcc/ChangeLog: > > * config/riscv/predicates.md (consecutive_bits_operand): > Implement new predicate. > > Signed-off-by: Philipp Tomsich > --- > > gcc/config/riscv/predicates.md | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index c37caa2502b..90db5dfcdd5 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -243,3 +243,14 @@ (define_predicate "const63_operand" > (define_predicate "imm5_operand" > (and (match_code "const_int") > (match_test "INTVAL (op) < 5"))) > + > +;; A CONST_INT operand that consists of a single run of consecutive set bits. > +(define_predicate "consecutive_bits_operand" > + (match_code "const_int") > +{ > + unsigned HOST_WIDE_INT val = UINTVAL (op); > + if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) > + return false; > + > + return true; > +}) > -- > 2.34.1 >