From: Kito Cheng <kito.cheng@gmail.com>
To: shihua@iscas.ac.cn
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
ben.marshall@pqshield.com,
Christoph Muellner <cmuellner@ventanamicro.com>,
Andrew Waterman <andrew@sifive.com>, jiawei <jiawei@iscas.ac.cn>,
mjos@iki.fi, Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension
Date: Tue, 1 Mar 2022 00:04:59 +0800 [thread overview]
Message-ID: <CA+yXCZBooy3v9tbGzhPAidv4ouO6218H1uZFXP1AqWicXQmDDA@mail.gmail.com> (raw)
In-Reply-To: <20220223094418.3518-2-shihua@iscas.ac.cn>
On Wed, Feb 23, 2022 at 5:46 PM <shihua@iscas.ac.cn> wrote:
>
> From: LiaoShihua <shihua@iscas.ac.cn>
>
>
> gcc/ChangeLog:
>
> * config/riscv/predicates.md (bs_operand): operand for bs
> (rnum_operand):
> * config/riscv/riscv.md: include crypto.md
> * config/riscv/crypto.md: New file.
>
> Co-Authored-By: Wu <siyu@isrc.iscas.ac.cn>
> ---
> gcc/config/riscv/crypto.md | 383 +++++++++++++++++++++++++++++++++
> gcc/config/riscv/predicates.md | 8 +
> gcc/config/riscv/riscv.md | 1 +
> 3 files changed, 392 insertions(+)
> create mode 100644 gcc/config/riscv/crypto.md
>
> diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
> new file mode 100644
> index 00000000000..591066fac3b
> --- /dev/null
> +++ b/gcc/config/riscv/crypto.md
> @@ -0,0 +1,383 @@
> +;; Machine description for K extension.
> +;; Copyright (C) 2022 Free Software Foundation, Inc.
> +;; Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn) and ShiHua Liao (shihua@iscas.ac.cn).
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3. If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +(define_c_enum "unspec" [
> + ;;ZBKB unspecs
> + UNSPEC_ROR
> + UNSPEC_ROL
We have standard patterns for ROR and ROL, so I think we don't need
unspec for those two.
...
> +(define_insn "riscv_ror_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")]
> + UNSPEC_ROR))]
> + "TARGET_ZBKB"
> + "ror\t%0,%1,%2")
>
> +
> +(define_insn "riscv_rol_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")]
> + UNSPEC_ROL))]
> + "TARGET_ZBKB"
> + "rol\t%0,%1,%2")
riscv_ror_<mode> and riscv_rol_<mode> can be removed.
> +
> +(define_insn "riscv_brev8_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_BREV8))]
> + "TARGET_ZBKB"
> + "brev8\t%0,%1")
> +
> +(define_insn "riscv_bswap<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_BSWAP))]
> + "TARGET_ZBKB"
> + "bswap\t%0,%1")
> +
> +(define_insn "riscv_zip"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
> + UNSPEC_ZIP))]
> + "TARGET_ZBKB && !TARGET_64BIT"
> + "zip\t%0,%1")
> +
> +(define_insn "riscv_unzip"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
> + UNSPEC_UNZIP))]
> + "TARGET_ZBKB && !TARGET_64BIT"
> + "unzip\t%0,%1")
> +
> +(define_insn "riscv_clmul_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")]
> + UNSPEC_CLMUL))]
> + "TARGET_ZBKC"
> + "clmul\t%0,%1,%2")
> +
> +(define_insn "riscv_clmulh_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")]
> + UNSPEC_CLMULH))]
> + "TARGET_ZBKC"
> + "clmulh\t%0,%1,%2")
> +
> +(define_insn "riscv_xperm8_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")]
> + UNSPEC_XPERM8))]
> + "TARGET_ZBKX"
> + "xperm8\t%0,%1,%2")
> +
> +(define_insn "riscv_xperm4_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")]
> + UNSPEC_XPERM4))]
> + "TARGET_ZBKX"
> + "xperm4\t%0,%1,%2")
> +
> +(define_insn "riscv_aes32dsi"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")
> + (match_operand:SI 3 "bs_operand" "i")]
> + UNSPEC_AES_DSI))]
> + "TARGET_ZKND && !TARGET_64BIT"
> + "aes32dsi\t%0,%1,%2,%3")
> +
> +(define_insn "riscv_aes32dsmi"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")
> + (match_operand:SI 3 "bs_operand" "i")]
> + UNSPEC_AES_DSMI))]
> + "TARGET_ZKND && !TARGET_64BIT"
> + "aes32dsmi\t%0,%1,%2,%3")
> +
> +(define_insn "riscv_aes64ds"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")
> + (match_operand:DI 2 "register_operand" "r")]
> + UNSPEC_AES_DS))]
> + "TARGET_ZKND && TARGET_64BIT"
> + "aes64ds\t%0,%1,%2")
> +
> +(define_insn "riscv_aes64dsm"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")
> + (match_operand:DI 2 "register_operand" "r")]
> + UNSPEC_AES_DSM))]
> + "TARGET_ZKND && TARGET_64BIT"
> + "aes64dsm\t%0,%1,%2")
> +
> +(define_insn "riscv_aes64im"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
> + UNSPEC_AES_IM))]
> + "TARGET_ZKND && TARGET_64BIT"
> + "aes64im\t%0,%1")
> +
> +(define_insn "riscv_aes64ks1i"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")
> + (match_operand:SI 2 "rnum_operand" "i")]
> + UNSPEC_AES_KS1I))]
> + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
> + "aes64ks1i\t%0,%1,%2")
> +
> +(define_insn "riscv_aes64ks2"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")
> + (match_operand:DI 2 "register_operand" "r")]
> + UNSPEC_AES_KS2))]
> + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
> + "aes64ks2\t%0,%1,%2")
> +
> +(define_insn "riscv_aes32esi"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")
> + (match_operand:SI 3 "bs_operand" "i")]
> + UNSPEC_AES_ESI))]
> + "TARGET_ZKNE && !TARGET_64BIT"
> + "aes32esi\t%0,%1,%2,%3")
> +
> +(define_insn "riscv_aes32esmi"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")
> + (match_operand:SI 3 "bs_operand" "i")]
> + UNSPEC_AES_ESMI))]
> + "TARGET_ZKNE && !TARGET_64BIT"
> + "aes32esmi\t%0,%1,%2,%3")
> +
> +(define_insn "riscv_aes64es"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")
> + (match_operand:DI 2 "register_operand" "r")]
> + UNSPEC_AES_ES))]
> + "TARGET_ZKNE && TARGET_64BIT"
> + "aes64es\t%0,%1,%2")
> +
> +(define_insn "riscv_aes64esm"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")
> + (match_operand:DI 2 "register_operand" "r")]
> + UNSPEC_AES_ESM))]
> + "TARGET_ZKNE && TARGET_64BIT"
> + "aes64esm\t%0,%1,%2")
> +
> +;; Zknh - SHA256
> +
> +(define_insn "riscv_sha256sig0_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_SHA_256_SIG0))]
> + "TARGET_ZKNH"
> + "sha256sig0\t%0,%1")
> +
> +(define_insn "riscv_sha256sig1_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_SHA_256_SIG1))]
> + "TARGET_ZKNH"
> + "sha256sig1\t%0,%1")
> +
> +(define_insn "riscv_sha256sum0_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_SHA_256_SUM0))]
> + "TARGET_ZKNH"
> + "sha256sum0\t%0,%1")
> +
> +(define_insn "riscv_sha256sum1_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_SHA_256_SUM1))]
> + "TARGET_ZKNH"
> + "sha256sum1\t%0,%1")
> +
> +(define_insn "riscv_sha512sig0h"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")]
> + UNSPEC_SHA_512_SIG0H))]
> + "TARGET_ZKNH && !TARGET_64BIT"
> + "sha512sig0h\t%0,%1,%2")
> +
> +(define_insn "riscv_sha512sig0l"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")]
> + UNSPEC_SHA_512_SIG0L))]
> + "TARGET_ZKNH && !TARGET_64BIT"
> + "sha512sig0l\t%0,%1,%2")
> +
> +(define_insn "riscv_sha512sig1h"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")]
> + UNSPEC_SHA_512_SIG1H))]
> + "TARGET_ZKNH && !TARGET_64BIT"
> + "sha512sig1h\t%0,%1,%2")
> +
> +(define_insn "riscv_sha512sig1l"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")]
> + UNSPEC_SHA_512_SIG1L))]
> + "TARGET_ZKNH && !TARGET_64BIT"
> + "sha512sig1l\t%0,%1,%2")
> +
> +(define_insn "riscv_sha512sum0r"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")]
> + UNSPEC_SHA_512_SUM0R))]
> + "TARGET_ZKNH && !TARGET_64BIT"
> + "sha512sum0r\t%0,%1,%2")
> +
> +(define_insn "riscv_sha512sum1r"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
> + (match_operand:SI 2 "register_operand" "r")]
> + UNSPEC_SHA_512_SUM1R))]
> + "TARGET_ZKNH && !TARGET_64BIT"
> + "sha512sum1r\t%0,%1,%2")
> +
> +(define_insn "riscv_sha512sig0"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
> + UNSPEC_SHA_512_SIG0))]
> + "TARGET_ZKNH && TARGET_64BIT"
> + "sha512sig0\t%0,%1")
> +
> +(define_insn "riscv_sha512sig1"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
> + UNSPEC_SHA_512_SIG1))]
> + "TARGET_ZKNH && TARGET_64BIT"
> + "sha512sig1\t%0,%1")
> +
> +(define_insn "riscv_sha512sum0"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
> + UNSPEC_SHA_512_SUM0))]
> + "TARGET_ZKNH && TARGET_64BIT"
> + "sha512sum0\t%0,%1")
> +
> +(define_insn "riscv_sha512sum1"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
> + UNSPEC_SHA_512_SUM1))]
> + "TARGET_ZKNH && TARGET_64BIT"
> + "sha512sum1\t%0,%1")
> +
> +(define_insn "riscv_sm3p0_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_SM3_P0))]
> + "TARGET_ZKSH"
> + "sm3p0\t%0,%1")
> +
> +(define_insn "riscv_sm3p1_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")]
> + UNSPEC_SM3_P1))]
> + "TARGET_ZKSH"
> + "sm3p1\t%0,%1")
> +
> +;; Zksed
> +
> +(define_insn "riscv_sm4ed_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")
> + (match_operand:SI 3 "bs_operand" "i")]
> + UNSPEC_SM4_ED))]
> + "TARGET_ZKSED"
> + "sm4ed\t%0,%1,%2,%3")
> +
> +(define_insn "riscv_sm4ks_<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (unspec:X [(match_operand:X 1 "register_operand" "r")
> + (match_operand:X 2 "register_operand" "r")
> + (match_operand:SI 3 "bs_operand" "i")]
> + UNSPEC_SM4_KS))]
> + "TARGET_ZKSED"
> + "sm4ks\t%0,%1,%2,%3")
> \ No newline at end of file
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index 97cdbdf053b..7e0e86651c0 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -239,3 +239,11 @@
> (define_predicate "const63_operand"
> (and (match_code "const_int")
> (match_test "INTVAL (op) == 63")))
> +
> +(define_predicate "bs_operand"
> + (and (match_code "const_int")
> + (match_test "INTVAL (op) < 4")))
> +
> +(define_predicate "rnum_operand"
> + (and (match_code "const_int")
> + (match_test "INTVAL (op) < 11")))
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index b3c5bce842a..59bfecb6341 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2864,6 +2864,7 @@
> [(set_attr "length" "12")])
>
> (include "bitmanip.md")
> +(include "crypto.md")
> (include "sync.md")
> (include "peephole.md")
> (include "pic.md")
> --
> 2.31.1.windows.1
>
next prev parent reply other threads:[~2022-02-28 16:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-23 9:44 [PATCH 0/5 V1] RISC-V:Implement Crypto extension's instruction patterns and it's intrinsics shihua
2022-02-23 9:44 ` [PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension shihua
2022-02-28 16:04 ` Kito Cheng [this message]
2022-02-23 9:44 ` [PATCH 2/5 V1] RISC-V:Implement built-in instructions " shihua
2022-02-23 9:44 ` [PATCH 3/5 V1] RISC-V:Implement intrinsics " shihua
2022-02-28 15:34 ` Kito Cheng
2022-02-23 9:44 ` [PATCH 4/5 V1] RISC-V:Implement testcases " shihua
2022-03-01 13:00 ` Kito Cheng
2022-03-01 13:49 ` Kito Cheng
2022-02-23 9:44 ` [PATCH 5/5 V1] RISC-V:Implement architecture extension test macros " shihua
2022-02-24 9:55 ` Kito Cheng
2022-02-28 15:56 ` Kito Cheng
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