From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id E63633858C83 for ; Mon, 28 Feb 2022 16:05:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E63633858C83 Received: by mail-ej1-x62f.google.com with SMTP id r13so25773067ejd.5 for ; Mon, 28 Feb 2022 08:05:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PjSgGWsqRStEaWnBFIUjVyxSPZM5c99Qywtq5GqSMC8=; b=HQTHzNThKU5E04bVi7FfzJNXWfkc+HH1vaMYQlgOYlXptjqIqT4CBQ0fTFGs1YQQgT dn9x/ZgufXr0fxyegBshN2XaSxefgRQUaQlUeJpSNhx0NasAezgg8ecKlgOSNT/TEE0o ga4OhfeAkAHXqqQfcQfpex9esxrbR/Y7a1v9NqWG0Y+SeLmNnsocyY3H2h2XRQKZ0/1H FcLHW2QpLe5/PxsEsyAhhzej8I+hAsEwsyTDT6x4m+uoFD7PslyIGJjrq2aZHKdyfZ+v /vVr4tEcbmEf/SNyGPuqacdQd1mTntK6MVLsMLAXwICwo4xL2U8E4T9dUuRwZKOEzB1C PYyQ== X-Gm-Message-State: AOAM53048gsEIAmsQJ9kVG5PjQUXlMnWX9yAvsNQsh1h2f5CHBQpuvzY mdh1V92BAZGctp2KOusUmz89nJV4aVPK7R+UW0c= X-Google-Smtp-Source: ABdhPJwzFXEaXXZYn1m0sunXJdmpMcoYBVsHQs+Pk1/mlpMol9sazMKMnd3cnbsq2rIe8S5BZm7Dy396QwOb6hfTIgI= X-Received: by 2002:a17:906:24cb:b0:6ce:b0a2:db5a with SMTP id f11-20020a17090624cb00b006ceb0a2db5amr15405077ejb.260.1646064310747; Mon, 28 Feb 2022 08:05:10 -0800 (PST) MIME-Version: 1.0 References: <20220223094418.3518-1-shihua@iscas.ac.cn> <20220223094418.3518-2-shihua@iscas.ac.cn> In-Reply-To: <20220223094418.3518-2-shihua@iscas.ac.cn> From: Kito Cheng Date: Tue, 1 Mar 2022 00:04:59 +0800 Message-ID: Subject: Re: [PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension To: shihua@iscas.ac.cn Cc: GCC Patches , ben.marshall@pqshield.com, Christoph Muellner , Andrew Waterman , jiawei , mjos@iki.fi, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Feb 2022 16:05:14 -0000 On Wed, Feb 23, 2022 at 5:46 PM wrote: > > From: LiaoShihua > > > gcc/ChangeLog: > > * config/riscv/predicates.md (bs_operand): operand for bs > (rnum_operand): > * config/riscv/riscv.md: include crypto.md > * config/riscv/crypto.md: New file. > > Co-Authored-By: Wu > --- > gcc/config/riscv/crypto.md | 383 +++++++++++++++++++++++++++++++++ > gcc/config/riscv/predicates.md | 8 + > gcc/config/riscv/riscv.md | 1 + > 3 files changed, 392 insertions(+) > create mode 100644 gcc/config/riscv/crypto.md > > diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md > new file mode 100644 > index 00000000000..591066fac3b > --- /dev/null > +++ b/gcc/config/riscv/crypto.md > @@ -0,0 +1,383 @@ > +;; Machine description for K extension. > +;; Copyright (C) 2022 Free Software Foundation, Inc. > +;; Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn) and ShiHua Liao (shihua@iscas.ac.cn). > + > +;; This file is part of GCC. > + > +;; GCC is free software; you can redistribute it and/or modify > +;; it under the terms of the GNU General Public License as published by > +;; the Free Software Foundation; either version 3, or (at your option) > +;; any later version. > + > +;; GCC is distributed in the hope that it will be useful, > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +;; GNU General Public License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; . > + > +(define_c_enum "unspec" [ > + ;;ZBKB unspecs > + UNSPEC_ROR > + UNSPEC_ROL We have standard patterns for ROR and ROL, so I think we don't need unspec for those two. ... > +(define_insn "riscv_ror_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r")] > + UNSPEC_ROR))] > + "TARGET_ZBKB" > + "ror\t%0,%1,%2") > > + > +(define_insn "riscv_rol_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r")] > + UNSPEC_ROL))] > + "TARGET_ZBKB" > + "rol\t%0,%1,%2") riscv_ror_ and riscv_rol_ can be removed. > + > +(define_insn "riscv_brev8_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_BREV8))] > + "TARGET_ZBKB" > + "brev8\t%0,%1") > + > +(define_insn "riscv_bswap" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_BSWAP))] > + "TARGET_ZBKB" > + "bswap\t%0,%1") > + > +(define_insn "riscv_zip" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] > + UNSPEC_ZIP))] > + "TARGET_ZBKB && !TARGET_64BIT" > + "zip\t%0,%1") > + > +(define_insn "riscv_unzip" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] > + UNSPEC_UNZIP))] > + "TARGET_ZBKB && !TARGET_64BIT" > + "unzip\t%0,%1") > + > +(define_insn "riscv_clmul_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r")] > + UNSPEC_CLMUL))] > + "TARGET_ZBKC" > + "clmul\t%0,%1,%2") > + > +(define_insn "riscv_clmulh_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r")] > + UNSPEC_CLMULH))] > + "TARGET_ZBKC" > + "clmulh\t%0,%1,%2") > + > +(define_insn "riscv_xperm8_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r")] > + UNSPEC_XPERM8))] > + "TARGET_ZBKX" > + "xperm8\t%0,%1,%2") > + > +(define_insn "riscv_xperm4_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r")] > + UNSPEC_XPERM4))] > + "TARGET_ZBKX" > + "xperm4\t%0,%1,%2") > + > +(define_insn "riscv_aes32dsi" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r") > + (match_operand:SI 3 "bs_operand" "i")] > + UNSPEC_AES_DSI))] > + "TARGET_ZKND && !TARGET_64BIT" > + "aes32dsi\t%0,%1,%2,%3") > + > +(define_insn "riscv_aes32dsmi" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r") > + (match_operand:SI 3 "bs_operand" "i")] > + UNSPEC_AES_DSMI))] > + "TARGET_ZKND && !TARGET_64BIT" > + "aes32dsmi\t%0,%1,%2,%3") > + > +(define_insn "riscv_aes64ds" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r") > + (match_operand:DI 2 "register_operand" "r")] > + UNSPEC_AES_DS))] > + "TARGET_ZKND && TARGET_64BIT" > + "aes64ds\t%0,%1,%2") > + > +(define_insn "riscv_aes64dsm" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r") > + (match_operand:DI 2 "register_operand" "r")] > + UNSPEC_AES_DSM))] > + "TARGET_ZKND && TARGET_64BIT" > + "aes64dsm\t%0,%1,%2") > + > +(define_insn "riscv_aes64im" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] > + UNSPEC_AES_IM))] > + "TARGET_ZKND && TARGET_64BIT" > + "aes64im\t%0,%1") > + > +(define_insn "riscv_aes64ks1i" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r") > + (match_operand:SI 2 "rnum_operand" "i")] > + UNSPEC_AES_KS1I))] > + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" > + "aes64ks1i\t%0,%1,%2") > + > +(define_insn "riscv_aes64ks2" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r") > + (match_operand:DI 2 "register_operand" "r")] > + UNSPEC_AES_KS2))] > + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" > + "aes64ks2\t%0,%1,%2") > + > +(define_insn "riscv_aes32esi" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r") > + (match_operand:SI 3 "bs_operand" "i")] > + UNSPEC_AES_ESI))] > + "TARGET_ZKNE && !TARGET_64BIT" > + "aes32esi\t%0,%1,%2,%3") > + > +(define_insn "riscv_aes32esmi" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r") > + (match_operand:SI 3 "bs_operand" "i")] > + UNSPEC_AES_ESMI))] > + "TARGET_ZKNE && !TARGET_64BIT" > + "aes32esmi\t%0,%1,%2,%3") > + > +(define_insn "riscv_aes64es" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r") > + (match_operand:DI 2 "register_operand" "r")] > + UNSPEC_AES_ES))] > + "TARGET_ZKNE && TARGET_64BIT" > + "aes64es\t%0,%1,%2") > + > +(define_insn "riscv_aes64esm" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r") > + (match_operand:DI 2 "register_operand" "r")] > + UNSPEC_AES_ESM))] > + "TARGET_ZKNE && TARGET_64BIT" > + "aes64esm\t%0,%1,%2") > + > +;; Zknh - SHA256 > + > +(define_insn "riscv_sha256sig0_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_SHA_256_SIG0))] > + "TARGET_ZKNH" > + "sha256sig0\t%0,%1") > + > +(define_insn "riscv_sha256sig1_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_SHA_256_SIG1))] > + "TARGET_ZKNH" > + "sha256sig1\t%0,%1") > + > +(define_insn "riscv_sha256sum0_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_SHA_256_SUM0))] > + "TARGET_ZKNH" > + "sha256sum0\t%0,%1") > + > +(define_insn "riscv_sha256sum1_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_SHA_256_SUM1))] > + "TARGET_ZKNH" > + "sha256sum1\t%0,%1") > + > +(define_insn "riscv_sha512sig0h" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r")] > + UNSPEC_SHA_512_SIG0H))] > + "TARGET_ZKNH && !TARGET_64BIT" > + "sha512sig0h\t%0,%1,%2") > + > +(define_insn "riscv_sha512sig0l" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r")] > + UNSPEC_SHA_512_SIG0L))] > + "TARGET_ZKNH && !TARGET_64BIT" > + "sha512sig0l\t%0,%1,%2") > + > +(define_insn "riscv_sha512sig1h" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r")] > + UNSPEC_SHA_512_SIG1H))] > + "TARGET_ZKNH && !TARGET_64BIT" > + "sha512sig1h\t%0,%1,%2") > + > +(define_insn "riscv_sha512sig1l" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r")] > + UNSPEC_SHA_512_SIG1L))] > + "TARGET_ZKNH && !TARGET_64BIT" > + "sha512sig1l\t%0,%1,%2") > + > +(define_insn "riscv_sha512sum0r" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r")] > + UNSPEC_SHA_512_SUM0R))] > + "TARGET_ZKNH && !TARGET_64BIT" > + "sha512sum0r\t%0,%1,%2") > + > +(define_insn "riscv_sha512sum1r" > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:SI 1 "register_operand" "r") > + (match_operand:SI 2 "register_operand" "r")] > + UNSPEC_SHA_512_SUM1R))] > + "TARGET_ZKNH && !TARGET_64BIT" > + "sha512sum1r\t%0,%1,%2") > + > +(define_insn "riscv_sha512sig0" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] > + UNSPEC_SHA_512_SIG0))] > + "TARGET_ZKNH && TARGET_64BIT" > + "sha512sig0\t%0,%1") > + > +(define_insn "riscv_sha512sig1" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] > + UNSPEC_SHA_512_SIG1))] > + "TARGET_ZKNH && TARGET_64BIT" > + "sha512sig1\t%0,%1") > + > +(define_insn "riscv_sha512sum0" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] > + UNSPEC_SHA_512_SUM0))] > + "TARGET_ZKNH && TARGET_64BIT" > + "sha512sum0\t%0,%1") > + > +(define_insn "riscv_sha512sum1" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] > + UNSPEC_SHA_512_SUM1))] > + "TARGET_ZKNH && TARGET_64BIT" > + "sha512sum1\t%0,%1") > + > +(define_insn "riscv_sm3p0_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_SM3_P0))] > + "TARGET_ZKSH" > + "sm3p0\t%0,%1") > + > +(define_insn "riscv_sm3p1_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r")] > + UNSPEC_SM3_P1))] > + "TARGET_ZKSH" > + "sm3p1\t%0,%1") > + > +;; Zksed > + > +(define_insn "riscv_sm4ed_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r") > + (match_operand:SI 3 "bs_operand" "i")] > + UNSPEC_SM4_ED))] > + "TARGET_ZKSED" > + "sm4ed\t%0,%1,%2,%3") > + > +(define_insn "riscv_sm4ks_" > + [(set (match_operand:X 0 "register_operand" "=r") > + (unspec:X [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "register_operand" "r") > + (match_operand:SI 3 "bs_operand" "i")] > + UNSPEC_SM4_KS))] > + "TARGET_ZKSED" > + "sm4ks\t%0,%1,%2,%3") > \ No newline at end of file > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 97cdbdf053b..7e0e86651c0 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -239,3 +239,11 @@ > (define_predicate "const63_operand" > (and (match_code "const_int") > (match_test "INTVAL (op) == 63"))) > + > +(define_predicate "bs_operand" > + (and (match_code "const_int") > + (match_test "INTVAL (op) < 4"))) > + > +(define_predicate "rnum_operand" > + (and (match_code "const_int") > + (match_test "INTVAL (op) < 11"))) > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index b3c5bce842a..59bfecb6341 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -2864,6 +2864,7 @@ > [(set_attr "length" "12")]) > > (include "bitmanip.md") > +(include "crypto.md") > (include "sync.md") > (include "peephole.md") > (include "pic.md") > -- > 2.31.1.windows.1 >