From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id 42F4B3858D35 for ; Mon, 8 Jan 2024 03:40:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 42F4B3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 42F4B3858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::62d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704685249; cv=none; b=WowCsdoCyHCwjAH80RTZeM5lpxtKeV0CX7I/7vutfyNxh3dDQcUBpQN90WIOImggiOUSc/umSpEKgYfNtsNYDa/NAVEqufkeykD3lfYwQ0yxHMoSRDPxqR4bpftzcZf0A58Fv35Hnj9TWIO7LP3DnKstj6MLXCmE3L5++QPNgx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704685249; c=relaxed/simple; bh=nasPb5m7AUzc915LOyFH/eZNAzwYceAYJkEp2JeSAmI=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=AVRCB48X+7pd/BC/nDeJiJ+xrxF2bobUiM4/jx3YfIFCXFoY+ExOwfw5Gqf2CGbYJRhugAJ5YseydCr/1PEtzY5bS4nnlo1Imcugvc8QfHQR9+LkCxGmF9d0AT75d4t6JrfQqMholvssJ439An+RAYNSGSN7U6CCV+WwqZAp2Ms= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a2ac304e526so19828466b.0 for ; Sun, 07 Jan 2024 19:40:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704685246; x=1705290046; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=fins4GGKw7iYOSFljw9mzH9KHLE7Hjk7CwO2mGIU58I=; b=D/5MurEl47tmXRN6UoFUKRo4uINIWe+YfIuQ1snuhkp0BO4eDH4/Ycp2g5/Dzkx1xo iQ7ChDDw7tBbWdwCCPy0/XKTZAKbct44uY6+rlHoNd93/ZDGV59BwNCPXyrZ2p+KV301 aaUmOL5js4MnH4C9KQ2anPR+qhObSiiduTU2AXP0Nj9ebZCzVWkAjoRu+fgcKWd7xvGe WBdin1KGCXIR5eVmJRkelTw91zXekf79soRsE6cD4cjMsU2lJu18lxk24en95bg1ifq6 cNCkQ3Hd0mHfMrWUdISqebBcygj4Lw2E/BhZFCVuq9ZA4KRof3N3k+fQGqau3Z1beQ3a UNRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704685246; x=1705290046; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fins4GGKw7iYOSFljw9mzH9KHLE7Hjk7CwO2mGIU58I=; b=bck1+TQ8NdNSzwl2SkU9o3ICmYtdZc9TtO8S+HRXY2kpTprab2mUMSgsy8PIawKyxO xApZoVUPlistWImK6MdiY1XtUaDohudWzEr8kFBEXYQcTPqSjUHc1NpvfRS2GOlLwaJ6 uY6QCX7AlS2umU106pmP5a4wvTKuUmLiX6nNcMlzfrgYMw/w0DSUGug9kxuHtzTiylWd uDkLrDWiI6r1bKmBFflltigklb4OkrnTcBFLDrm8zvuJtmERONM2h6tuzY+ITY4Yo8jL P8x0iBEZMN9/pvwoCXmDyb42u3g6Jir8AejsJ4eNBQzHuDFLMwqxYkOWYUq1b/S6t3Fe x4Yw== X-Gm-Message-State: AOJu0YwUh0lbf3Zko+6bhHzrPnDBci2KlRBMjLe5/VoBiZ3GAA9MXLO3 HfkBazQEfmFAFZiN/aR2eHEdRl8cNW7D8h78/lA= X-Google-Smtp-Source: AGHT+IGWki0K1Rd0wiz4ozXOBvPbk43a4BsrlYrtmdce+CB0EJoiqJLvq0XzF80NRkHiQhYP2FPd9pJdgDYCP1mPc7o= X-Received: by 2002:a17:906:7704:b0:a23:4b44:7dcc with SMTP id q4-20020a170906770400b00a234b447dccmr1208584ejm.33.1704685245409; Sun, 07 Jan 2024 19:40:45 -0800 (PST) MIME-Version: 1.0 References: <32c05834-52b8-4e41-be07-886190217c3d.cooper.joshua@linux.alibaba.com> In-Reply-To: <32c05834-52b8-4e41-be07-886190217c3d.cooper.joshua@linux.alibaba.com> From: Kito Cheng Date: Mon, 8 Jan 2024 11:40:33 +0800 Message-ID: Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. To: joshua Cc: "juzhe.zhong@rivai.ai" , jeffreyalaw , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , "christoph.muellner" , jinma , "cooper.qu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: It depends on the timing when you send out the v1 patch to the mailing list, not the timing of when to merge, but of course it's case by case, I would say no IF it's still not ready when time is the end of Feb for this kind of big patch set. On Mon, Jan 8, 2024 at 11:17=E2=80=AFAM joshua wrote: > > Hi Kito, > > Thank you for your support. > So even during stage 4, we can merge this for GCC 14? > > > > > > ------------------------------------------------------------------ > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9AKito Cheng > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A2024=E5=B9=B41=E6=9C=888=E6= =97=A5(=E6=98=9F=E6=9C=9F=E4=B8=80) 11:06 > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9Ajoshua > =E6=8A=84=E3=80=80=E9=80=81=EF=BC=9A"juzhe.zhong@rivai.ai"; jeffreyalaw; "gcc-patches"; Jim Wilson; palmer;= andrew; "philipp.tomsich"; "c= hristoph.muellner"; jinma; "cooper.qu" > =E4=B8=BB=E3=80=80=E9=A2=98=EF=BC=9ARe: Re: [PATCH v4] RISC-V: Adds the p= refix "th." for the instructions of XTheadVector. > > > I am ok with merging this for GCC 14, as we discussed several times in > the RISC-V GCC sync up meeting, I think at least we reach consensus > among Jeff Law, Palmer Dabbelt and me. > > But please be careful: don't break anything for standard vector stuff. > > On Mon, Jan 8, 2024 at 10:11 AM joshua = wrote: > > > > Hi Juzhe, > > > > Stage 3 will close today and there are still some patches that > > haven't been reviewed left. > > So is it possible to get xtheadvector merged in GCC-14? > > We emailed Kito regarding this, but haven't got any reply yet. > > > > Joshua > > > > > > > > > > > > > > ------------------------------------------------------------------ > > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9Ajuzhe.zhong@rivai.ai > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A2024=E5=B9=B41=E6=9C=884= =E6=97=A5(=E6=98=9F=E6=9C=9F=E5=9B=9B) 17:18 > > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9A"cooper.joshua"; jeffreyalaw; "gcc-patches" > > =E6=8A=84 =E9=80=81=EF=BC=9AJim Wilson; palme= r; andrew; "philipp.tomsich"; "christoph.muellner"; jinm= a; "cooper.qu" > > =E4=B8=BB =E9=A2=98=EF=BC=9ARe: Re: [PATCH v4] RISC-V: Adds the prefix = "th." for the instructions of XTheadVector. > > > > > > \ No newline at end of file > > Each file needs newline. > > > > > > I am not able to review arch stuff. This needs kito. > > > > > > Besides, Andrew Pinski want us defer theadvector to GCC-15. > > > > > > I have no strong opinion here. > > > > > > juzhe.zhong@rivai.ai > > > > > > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9A joshua > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A 2024-01-04 17:15 > > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9A =E9=92=9F=E5=B1=85=E5=93=B2; Jeff = Law; gcc-patches > > =E6=8A=84=E9=80=81=EF=BC=9A jim.wilson.gcc; palmer; andrew; philipp.tom= sich; Christoph M=C3=BCllner; jinma; Cooper Qu > > =E4=B8=BB=E9=A2=98=EF=BC=9A Re=EF=BC=9ARe: [PATCH v4] RISC-V: Adds the = prefix "th." for the instructions of XTheadVector. > > > > Hi Juzhe, > > > > So is the following patch that this patch relies on OK to commit? > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > > Joshua > > > > > > > > > > ------------------------------------------------------------------ > > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9A=E9=92=9F=E5=B1=85=E5=93=B2 > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A2024=E5=B9=B41=E6=9C=882= =E6=97=A5(=E6=98=9F=E6=9C=9F=E4=BA=8C) 06:57 > > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9AJeff Law; "c= ooper.joshua"; "gcc-patches" > > =E6=8A=84 =E9=80=81=EF=BC=9A"jim.wilson.gcc";= palmer; andrew; "philipp.tomsich"; "Christoph M=C3=BCllner"; jinma; Cooper Qu > > =E4=B8=BB =E9=A2=98=EF=BC=9ARe: Re: [PATCH v4] RISC-V: Adds the prefix = "th." for the instructions of XTheadVector. > > > > > > This is Ok from my side. > > But before commit this patch, I think we need this patch first: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > > > > I will be back to work so I will take a look at other patches today. > > juzhe.zhong@rivai.ai > > > > > > From: Jeff Law > > Date: 2024-01-01 01:43 > > To: Jun Sha (Joshua); gcc-patches > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner= ; juzhe.zhong; Jin Ma; Xianmiao Qu > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructi= ons of XTheadVector. > > > > > > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > > This patch adds th. prefix to all XTheadVector instructions by > > > implementing new assembly output functions. We only check the > > > prefix is 'v', so that no extra attribute is needed. > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > > New function to add assembler insn code prefix/suffix. > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > > > Co-authored-by: Jin Ma > > > Co-authored-by: Xianmiao Qu > > > Co-authored-by: Christoph M=C3=BCllner > > > --- > > > gcc/config/riscv/riscv-protos.h | 1 + > > > gcc/config/riscv/riscv.cc | 14 +++++++++++= +++ > > > gcc/config/riscv/riscv.h | 4 ++++ > > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 +++++++++++= + > > > 4 files changed, 31 insertions(+) > > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/= prefix.c > > > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv= -protos.h > > > index 31049ef7523..5ea54b45703 100644 > > > --- a/gcc/config/riscv/riscv-protos.h > > > +++ b/gcc/config/riscv/riscv-protos.h > > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > > }; > > > > > > /* Routines implemented in riscv.cc. */ > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, cons= t char *p); > > > extern enum riscv_symbol_type riscv_classify_symbolic_expression (r= tx); > > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type = *); > > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > > --- a/gcc/config/riscv/riscv.cc > > > +++ b/gcc/config/riscv/riscv.cc > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode= ) > > > return lmul; > > > } > > > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > > + emitting an opcode. */ > > > +const char * > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > > +{ > > > + /* We need to add th. prefix to all the xtheadvector > > > + insturctions here.*/ > > > + if (TARGET_XTHEADVECTOR && current_output_insn !=3D NULL_RTX && > > > + p[0] =3D=3D 'v') > > > + fputs ("th.", asm_out_file); > > > + > > > + return p; > > Just a formatting nit. The GNU standards break lines before the > > operator, not after. So > > if (TARGET_XTHEADVECTOR > > && current_output_insn !=3D NULL > > && p[0] =3D=3D 'v') > > > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not > > NULL_RTX. > > > > Neither of these nits require a new version for review. Just fix them. > > > > If Juzhe is fine with this, so am I. We can refine it if necessary lat= er. > > > > jeff > > > > > > > > > >