From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 6F23B385701D for ; Tue, 11 Oct 2022 02:36:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6F23B385701D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62b.google.com with SMTP id nb11so28508011ejc.5 for ; Mon, 10 Oct 2022 19:36:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=SSrfJ44muy65JM6nBeU7LOnbm/1e8rO3ET+3sk0Y99s=; b=GX4fRXAS2VqFYg5dmI6Lyo14fFV3ACjkAhvotPi+2Y2OTMSRrGV5uQkCeg80cRvfcZ aW4TFU5VzwThr+/7pRdP+nTMNJ8n/ZZ0XC1Z9vxPqV7FfFZ4RQbQMCwaiSPl56R43kBe GhbnraMXVa+p4m0+/CEns4UPcloT/e/+l5PQ9rUFqiPBWt60txDMBwXfgxcNXBAj/3Oa QRGMs+Zr0216tK9LrYh9NvfjneKeol7YmikWJFq8jBfQsmYcpP6rvMYzvSfhlClSQhsM ZTI/TCRm/woR1iA6nZR2iCVrcfJKtIs9X8JBCjjqjnJnmSHwuUvRCoflSJ6Inx69IKjc aFOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=SSrfJ44muy65JM6nBeU7LOnbm/1e8rO3ET+3sk0Y99s=; b=SKvAnIf2XZolpJQyzeInYvir5bpMRm+RJpIojGlt0TfC+XLlQmQKLC0/cKLSShztFK G9N6XfF5h7S1JtrUKsTQ4mNYl4Q0Pv0Wx7jsiFncpAAnpimEn4ScgJnalWOZ5S2Rw2la vlDdksqZrhuhDxoVTZFokc8seamhPOWhGSys+vHHZYzYc98/Bt/5LM/M4PYuHonn4PH+ 4TiT/Lvfq+raKDihV5+0BXCbBD+jYjwhghfbm3yl25LEAuPuebHUa0PXdKayTO0xmB7b OMZRd0pJVjqSIO6TW6lMRF1FiVwcNY/BBfAmiAjVZWSi0cRGwrObt8sE1NvnENRQ1H9P 3Ljw== X-Gm-Message-State: ACrzQf2IqPsO1tgFaKz0zfG+5w7B2Ggcfo55wLbqrlexOi6FPrv6HjDk nKAsvO+2KplzspzVtKbhABdmVYSDHvTNdEcN294= X-Google-Smtp-Source: AMsMyM7dWTHOpt2rqVqR65ZdyQhDHVby6BLgsFPEi7naAmb4tIad1HOTKS/MeBlgpGPGdPeg9i2iPN/MRb+q2WpKkag= X-Received: by 2002:a17:907:6e93:b0:78d:dff1:71e3 with SMTP id sh19-20020a1709076e9300b0078ddff171e3mr367317ejc.94.1665455773973; Mon, 10 Oct 2022 19:36:13 -0700 (PDT) MIME-Version: 1.0 References: <20221010135721.173181-1-juzhe.zhong@rivai.ai> In-Reply-To: <20221010135721.173181-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Tue, 11 Oct 2022 10:36:02 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks :) On Mon, Oct 10, 2022 at 9:58 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move from config/riscv/riscv-vector-builtins.h. > (DEF_RVV_TYPE): Change USER_NAME to NAME. > (register_vector_type): Change user_name to name. > * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Change USER_NAME to NAME. > * config/riscv/riscv-vector-builtins.h (struct vector_type_info): Move to riscv-vector-builtins.cc. > (DEF_RVV_TYPE): Change USER_NAME to NAME. > > --- > gcc/config/riscv/riscv-vector-builtins.cc | 28 +++++++++++++++++----- > gcc/config/riscv/riscv-vector-builtins.def | 2 +- > gcc/config/riscv/riscv-vector-builtins.h | 20 ++-------------- > 3 files changed, 25 insertions(+), 25 deletions(-) > > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc > index 0096e32f5e4..7033b1fc176 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -50,10 +50,26 @@ using namespace riscv_vector; > > namespace riscv_vector { > > +/* Static information about each vector type. */ > +struct vector_type_info > +{ > + /* The name of the type as declared by riscv_vector.h > + which is recommend to use. For example: 'vint32m1_t'. */ > + const char *name; > + > + /* ABI name of vector type. The type is always available > + under this name, even when riscv_vector.h isn't included. > + For example: '__rvv_int32m1_t'. */ > + const char *abi_name; > + > + /* The C++ mangling of ABI_NAME. */ > + const char *mangled_name; > +}; > + > /* Information about each RVV type. */ > static CONSTEXPR const vector_type_info vector_types[] = { > -#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, ARGS...) \ > - {#USER_NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME}, > +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, ARGS...) \ > + {#NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME}, > #include "riscv-vector-builtins.def" > }; > > @@ -151,14 +167,14 @@ register_builtin_types () > = TARGET_64BIT ? unsigned_intSI_type_node : long_unsigned_type_node; > > machine_mode mode; > -#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \ > +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \ > VECTOR_MODE_MIN_VLEN_32) \ > mode = TARGET_MIN_VLEN > 32 ? VECTOR_MODE##mode \ > : VECTOR_MODE_MIN_VLEN_32##mode; \ > - scalar_types[VECTOR_TYPE_##USER_NAME] \ > + scalar_types[VECTOR_TYPE_##NAME] \ > = riscv_v_ext_enabled_vector_mode_p (mode) ? SCALAR_TYPE##_type_node \ > : NULL_TREE; \ > - vector_modes[VECTOR_TYPE_##USER_NAME] \ > + vector_modes[VECTOR_TYPE_##NAME] \ > = riscv_v_ext_enabled_vector_mode_p (mode) ? mode : VOIDmode; > #include "riscv-vector-builtins.def" > > @@ -198,7 +214,7 @@ register_vector_type (vector_type_index type) > is disabled according to '-march'. */ > if (!vectype) > return; > - tree id = get_identifier (vector_types[type].user_name); > + tree id = get_identifier (vector_types[type].name); > tree decl = build_decl (input_location, TYPE_DECL, id, vectype); > decl = lang_hooks.decls.pushdecl (decl); > > diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def > index a9001b3b496..664734b881b 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.def > +++ b/gcc/config/riscv/riscv-vector-builtins.def > @@ -32,7 +32,7 @@ along with GCC; see the file COPYING3. If not see > TARGET_MIN_VLEN > 32. Otherwise the machine mode is VNx1SImode. */ > > #ifndef DEF_RVV_TYPE > -#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \ > +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \ > VECTOR_MODE_MIN_VLEN_32) > #endif > > diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h > index 6ca0b073964..ec85e0b1320 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.h > +++ b/gcc/config/riscv/riscv-vector-builtins.h > @@ -26,28 +26,12 @@ namespace riscv_vector { > /* This is for segment instructions. */ > const unsigned int MAX_TUPLE_SIZE = 8; > > -/* Static information about each vector type. */ > -struct vector_type_info > -{ > - /* The name of the type as declared by riscv_vector.h > - which is recommend to use. For example: 'vint32m1_t'. */ > - const char *user_name; > - > - /* ABI name of vector type. The type is always available > - under this name, even when riscv_vector.h isn't included. > - For example: '__rvv_int32m1_t'. */ > - const char *abi_name; > - > - /* The C++ mangling of ABI_NAME. */ > - const char *mangled_name; > -}; > - > /* Enumerates the RVV types, together called > "vector types" for brevity. */ > enum vector_type_index > { > -#define DEF_RVV_TYPE(USER_NAME, ABI_NAME, NCHARS, ARGS...) \ > - VECTOR_TYPE_##USER_NAME, > +#define DEF_RVV_TYPE(NAME, ABI_NAME, NCHARS, ARGS...) \ > + VECTOR_TYPE_##NAME, > #include "riscv-vector-builtins.def" > NUM_VECTOR_TYPES > }; > -- > 2.36.1 >