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Sat, 18 Nov 2023 02:06:38 -0800 (PST) MIME-Version: 1.0 References: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> <20231118042627.3598-1-cooper.joshua@linux.alibaba.com> In-Reply-To: <20231118042627.3598-1-cooper.joshua@linux.alibaba.com> From: Kito Cheng Date: Sat, 18 Nov 2023 18:06:20 +0800 Message-ID: Subject: Re: [PATCH v2 1/9] RISC-V: minimal support for xtheadvector To: "Jun Sha (Joshua)" Cc: gcc-patches@gcc.gnu.org, jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Nov 18, 2023 at 12:27=E2=80=AFPM Jun Sha (Joshua) wrote: > > This patch is to introduce basic XTheadVector support > (march string parsing and a test for __riscv_xtheadvector) > according to https://github.com/T-head-Semi/thead-extension-spec/ > > Contributors: > Jun Sha (Joshua) > Jin Ma > Christoph M=C3=BCllner > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc > (riscv_subset_list::parse): : Add new vendor extension. > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): > Add test marco. > * config/riscv/riscv.opt: Add new mask. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test. > * gcc.target/riscv/rvv/xtheadvector.c: New test. > --- > gcc/common/config/riscv/riscv-common.cc | 10 ++++++++++ > gcc/config/riscv/riscv-c.cc | 4 ++++ > gcc/config/riscv/riscv.opt | 2 ++ > .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +++++++++++ > gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c | 13 +++++++++++++ > 5 files changed, 40 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_in= trinsic.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/= riscv/riscv-common.cc > index 526dbb7603b..914924171fd 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -75,6 +75,8 @@ static const riscv_implied_info_t riscv_implied_info[] = =3D > > {"v", "zvl128b"}, > {"v", "zve64d"}, > + {"xtheadvector", "zvl128b"}, > + {"xtheadvector", "zve64d"}, ^^^ don't imply zve64d, it will mix V 1.0 together, I know why you want to do that, so I have given some suggestions below. > > {"zve32f", "f"}, > {"zve64f", "f"}, > @@ -325,6 +327,7 @@ static const struct riscv_ext_version riscv_ext_versi= on_table[] =3D > {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0}, > > {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, > > @@ -1495,6 +1498,10 @@ riscv_subset_list::parse (const char *arch, locati= on_t loc) > error_at (loc, "%<-march=3D%s%>: z*inx conflicts with floating-point= " > "extensions", arch); > > + if (subset_list->lookup ("v") && subset_list->lookup ("xtheadvector")) > + error_at (loc, "%<-march=3D%s%>: xtheadvector conflicts with vector = " > + "extensions", arch); > + > /* 'H' hypervisor extension requires base ISA with 32 registers. */ > if (subset_list->lookup ("e") && subset_list->lookup ("h")) > error_at (loc, "%<-march=3D%s%>: h extension requires i extension", = arch); > @@ -1680,6 +1687,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_= table[] =3D > {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMI= DX}, > {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMP= AIR}, > {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC= }, > + {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECT= OR}, > + {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V}, > + {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR}, Add following two line then you don't need zve64d {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN= _64}, {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, > > {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTA= NACONDOPS}, >