From: Kito Cheng <kito.cheng@gmail.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com,
kito.cheng@sifive.com, rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Support VLS shift vectorization
Date: Tue, 8 Aug 2023 10:18:10 +0800 [thread overview]
Message-ID: <CA+yXCZBsnJZi1f03EWO7u=0r_ZT=gAjf8ZwiLt+QTnNhqubh7w@mail.gmail.com> (raw)
In-Reply-To: <20230808013709.168452-1-juzhe.zhong@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 20020 bytes --]
Lgtm
Juzhe-Zhong <juzhe.zhong@rivai.ai>於 2023年8月8日 週二，09:37寫道：
> After this patch, this following case will be well optimized:
> #include "riscv_vector.h"
>
> #define DEF_OP_VV(PREFIX, NUM, TYPE, OP)
> \
> void __attribute__ ((noinline, noclone))
> \
> PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict
> c) \
> {
> \
> for (int i = 0; i < NUM; ++i)
> \
> a[i] = b[i] OP c[i];
> \
> }
>
> DEF_OP_VV (shift, 16, int32_t, >>)
>
> ASM:
> shift_int32_t16:
> vsetivli zero,16,e32,mf2,ta,ma
> vle32.v v1,0(a1)
> vle32.v v2,0(a2)
> vsra.vv v1,v1,v2
> vse32.v v1,0(a0)
> ret
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Add VLS shift.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS shift.
> * gcc.target/riscv/rvv/autovec/vls/shift-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/shift-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/shift-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/shift-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/shift-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/shift-6.c: New test.
>
> ---
> gcc/config/riscv/autovec.md | 14 ++---
> .../gcc.target/riscv/rvv/autovec/vls/def.h | 8 +++
> .../riscv/rvv/autovec/vls/shift-1.c | 57 ++++++++++++++++++
> .../riscv/rvv/autovec/vls/shift-2.c | 57 ++++++++++++++++++
> .../riscv/rvv/autovec/vls/shift-3.c | 58 +++++++++++++++++++
> .../riscv/rvv/autovec/vls/shift-4.c | 57 ++++++++++++++++++
> .../riscv/rvv/autovec/vls/shift-5.c | 57 ++++++++++++++++++
> .../riscv/rvv/autovec/vls/shift-6.c | 57 ++++++++++++++++++
> 8 files changed, 358 insertions(+), 7 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 5e97ccba3b3..6cb5fa3ed27 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -400,9 +400,9 @@
> ;;
> -------------------------------------------------------------------------
>
> (define_insn_and_split "<optab><mode>3"
> - [(set (match_operand:VI 0 "register_operand" "=vr")
> - (any_shift:VI
> - (match_operand:VI 1 "register_operand" " vr")
> + [(set (match_operand:V_VLSI 0 "register_operand" "=vr")
> + (any_shift:V_VLSI
> + (match_operand:V_VLSI 1 "register_operand" " vr")
> (match_operand:<VEL> 2 "csr_operand" " rK")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> @@ -425,10 +425,10 @@
> ;;
> -------------------------------------------------------------------------
>
> (define_insn_and_split "v<optab><mode>3"
> - [(set (match_operand:VI 0 "register_operand" "=vr,vr")
> - (any_shift:VI
> - (match_operand:VI 1 "register_operand" " vr,vr")
> - (match_operand:VI 2 "vector_shift_operand" " vr,vk")))]
> + [(set (match_operand:V_VLSI 0 "register_operand" "=vr,vr")
> + (any_shift:V_VLSI
> + (match_operand:V_VLSI 1 "register_operand" " vr,vr")
> + (match_operand:V_VLSI 2 "vector_shift_operand" " vr,vk")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> index 2ef84be3b63..33916ff0698 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> @@ -134,3 +134,11 @@ typedef double v512df __attribute__ ((vector_size
> (4096)));
> for (int i = 0; i < NUM; ++i)
> \
> a[i] = b[i] OP c[i] ? b[i] : c[i];
> \
> }
> +
> +#define DEF_OP_VI_7(PREFIX, NUM, TYPE, OP)
> \
> + void __attribute__ ((noinline, noclone))
> \
> + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE
> *restrict c) \
> + {
> \
> + for (int i = 0; i < NUM; ++i)
> \
> + a[i] = b[i] OP 7;
> \
> + }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
> new file mode 100644
> index 00000000000..e57a0b6bdf3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
> @@ -0,0 +1,57 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
> +
> +#include "def.h"
> +
> +DEF_OP_VV (shift, 1, int8_t, >>)
> +DEF_OP_VV (shift, 2, int8_t, >>)
> +DEF_OP_VV (shift, 4, int8_t, >>)
> +DEF_OP_VV (shift, 8, int8_t, >>)
> +DEF_OP_VV (shift, 16, int8_t, >>)
> +DEF_OP_VV (shift, 32, int8_t, >>)
> +DEF_OP_VV (shift, 64, int8_t, >>)
> +DEF_OP_VV (shift, 128, int8_t, >>)
> +DEF_OP_VV (shift, 256, int8_t, >>)
> +DEF_OP_VV (shift, 512, int8_t, >>)
> +DEF_OP_VV (shift, 1024, int8_t, >>)
> +DEF_OP_VV (shift, 2048, int8_t, >>)
> +DEF_OP_VV (shift, 4096, int8_t, >>)
> +
> +DEF_OP_VV (shift, 1, int16_t, >>)
> +DEF_OP_VV (shift, 2, int16_t, >>)
> +DEF_OP_VV (shift, 4, int16_t, >>)
> +DEF_OP_VV (shift, 8, int16_t, >>)
> +DEF_OP_VV (shift, 16, int16_t, >>)
> +DEF_OP_VV (shift, 32, int16_t, >>)
> +DEF_OP_VV (shift, 64, int16_t, >>)
> +DEF_OP_VV (shift, 128, int16_t, >>)
> +DEF_OP_VV (shift, 256, int16_t, >>)
> +DEF_OP_VV (shift, 512, int16_t, >>)
> +DEF_OP_VV (shift, 1024, int16_t, >>)
> +DEF_OP_VV (shift, 2048, int16_t, >>)
> +
> +DEF_OP_VV (shift, 1, int32_t, >>)
> +DEF_OP_VV (shift, 2, int32_t, >>)
> +DEF_OP_VV (shift, 4, int32_t, >>)
> +DEF_OP_VV (shift, 8, int32_t, >>)
> +DEF_OP_VV (shift, 16, int32_t, >>)
> +DEF_OP_VV (shift, 32, int32_t, >>)
> +DEF_OP_VV (shift, 64, int32_t, >>)
> +DEF_OP_VV (shift, 128, int32_t, >>)
> +DEF_OP_VV (shift, 256, int32_t, >>)
> +DEF_OP_VV (shift, 512, int32_t, >>)
> +DEF_OP_VV (shift, 1024, int32_t, >>)
> +
> +DEF_OP_VV (shift, 1, int64_t, >>)
> +DEF_OP_VV (shift, 2, int64_t, >>)
> +DEF_OP_VV (shift, 4, int64_t, >>)
> +DEF_OP_VV (shift, 8, int64_t, >>)
> +DEF_OP_VV (shift, 16, int64_t, >>)
> +DEF_OP_VV (shift, 32, int64_t, >>)
> +DEF_OP_VV (shift, 64, int64_t, >>)
> +DEF_OP_VV (shift, 128, int64_t, >>)
> +DEF_OP_VV (shift, 256, int64_t, >>)
> +DEF_OP_VV (shift, 512, int64_t, >>)
> +
> +/* { dg-final { scan-assembler-times
> {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
> new file mode 100644
> index 00000000000..9d1fa64232c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
> @@ -0,0 +1,57 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
> +
> +#include "def.h"
> +
> +DEF_OP_VV (shift, 1, uint8_t, >>)
> +DEF_OP_VV (shift, 2, uint8_t, >>)
> +DEF_OP_VV (shift, 4, uint8_t, >>)
> +DEF_OP_VV (shift, 8, uint8_t, >>)
> +DEF_OP_VV (shift, 16, uint8_t, >>)
> +DEF_OP_VV (shift, 32, uint8_t, >>)
> +DEF_OP_VV (shift, 64, uint8_t, >>)
> +DEF_OP_VV (shift, 128, uint8_t, >>)
> +DEF_OP_VV (shift, 256, uint8_t, >>)
> +DEF_OP_VV (shift, 512, uint8_t, >>)
> +DEF_OP_VV (shift, 1024, uint8_t, >>)
> +DEF_OP_VV (shift, 2048, uint8_t, >>)
> +DEF_OP_VV (shift, 4096, uint8_t, >>)
> +
> +DEF_OP_VV (shift, 1, uint16_t, >>)
> +DEF_OP_VV (shift, 2, uint16_t, >>)
> +DEF_OP_VV (shift, 4, uint16_t, >>)
> +DEF_OP_VV (shift, 8, uint16_t, >>)
> +DEF_OP_VV (shift, 16, uint16_t, >>)
> +DEF_OP_VV (shift, 32, uint16_t, >>)
> +DEF_OP_VV (shift, 64, uint16_t, >>)
> +DEF_OP_VV (shift, 128, uint16_t, >>)
> +DEF_OP_VV (shift, 256, uint16_t, >>)
> +DEF_OP_VV (shift, 512, uint16_t, >>)
> +DEF_OP_VV (shift, 1024, uint16_t, >>)
> +DEF_OP_VV (shift, 2048, uint16_t, >>)
> +
> +DEF_OP_VV (shift, 1, uint32_t, >>)
> +DEF_OP_VV (shift, 2, uint32_t, >>)
> +DEF_OP_VV (shift, 4, uint32_t, >>)
> +DEF_OP_VV (shift, 8, uint32_t, >>)
> +DEF_OP_VV (shift, 16, uint32_t, >>)
> +DEF_OP_VV (shift, 32, uint32_t, >>)
> +DEF_OP_VV (shift, 64, uint32_t, >>)
> +DEF_OP_VV (shift, 128, uint32_t, >>)
> +DEF_OP_VV (shift, 256, uint32_t, >>)
> +DEF_OP_VV (shift, 512, uint32_t, >>)
> +DEF_OP_VV (shift, 1024, uint32_t, >>)
> +
> +DEF_OP_VV (shift, 1, uint64_t, >>)
> +DEF_OP_VV (shift, 2, uint64_t, >>)
> +DEF_OP_VV (shift, 4, uint64_t, >>)
> +DEF_OP_VV (shift, 8, uint64_t, >>)
> +DEF_OP_VV (shift, 16, uint64_t, >>)
> +DEF_OP_VV (shift, 32, uint64_t, >>)
> +DEF_OP_VV (shift, 64, uint64_t, >>)
> +DEF_OP_VV (shift, 128, uint64_t, >>)
> +DEF_OP_VV (shift, 256, uint64_t, >>)
> +DEF_OP_VV (shift, 512, uint64_t, >>)
> +
> +/* { dg-final { scan-assembler-times
> {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> new file mode 100644
> index 00000000000..98822b15657
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> @@ -0,0 +1,58 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
> +
> +#include "def.h"
> +
> +DEF_OP_VV (shift, 1, int8_t, <<)
> +DEF_OP_VV (shift, 2, int8_t, <<)
> +DEF_OP_VV (shift, 4, int8_t, <<)
> +DEF_OP_VV (shift, 8, int8_t, <<)
> +DEF_OP_VV (shift, 16, int8_t, <<)
> +DEF_OP_VV (shift, 32, int8_t, <<)
> +DEF_OP_VV (shift, 64, int8_t, <<)
> +DEF_OP_VV (shift, 128, int8_t, <<)
> +DEF_OP_VV (shift, 256, int8_t, <<)
> +DEF_OP_VV (shift, 512, int8_t, <<)
> +DEF_OP_VV (shift, 1024, int8_t, <<)
> +DEF_OP_VV (shift, 2048, int8_t, <<)
> +DEF_OP_VV (shift, 4096, int8_t, <<)
> +
> +DEF_OP_VV (shift, 1, int16_t, <<)
> +DEF_OP_VV (shift, 2, int16_t, <<)
> +DEF_OP_VV (shift, 4, int16_t, <<)
> +DEF_OP_VV (shift, 8, int16_t, <<)
> +DEF_OP_VV (shift, 16, int16_t, <<)
> +DEF_OP_VV (shift, 32, int16_t, <<)
> +DEF_OP_VV (shift, 64, int16_t, <<)
> +DEF_OP_VV (shift, 128, int16_t, <<)
> +DEF_OP_VV (shift, 256, int16_t, <<)
> +DEF_OP_VV (shift, 512, int16_t, <<)
> +DEF_OP_VV (shift, 1024, int16_t, <<)
> +DEF_OP_VV (shift, 2048, int16_t, <<)
> +
> +DEF_OP_VV (shift, 1, int32_t, <<)
> +DEF_OP_VV (shift, 2, int32_t, <<)
> +DEF_OP_VV (shift, 4, int32_t, <<)
> +DEF_OP_VV (shift, 8, int32_t, <<)
> +DEF_OP_VV (shift, 16, int32_t, <<)
> +DEF_OP_VV (shift, 32, int32_t, <<)
> +DEF_OP_VV (shift, 64, int32_t, <<)
> +DEF_OP_VV (shift, 128, int32_t, <<)
> +DEF_OP_VV (shift, 256, int32_t, <<)
> +DEF_OP_VV (shift, 512, int32_t, <<)
> +DEF_OP_VV (shift, 1024, int32_t, <<)
> +
> +DEF_OP_VV (shift, 1, int64_t, <<)
> +DEF_OP_VV (shift, 2, int64_t, <<)
> +DEF_OP_VV (shift, 4, int64_t, <<)
> +DEF_OP_VV (shift, 8, int64_t, <<)
> +DEF_OP_VV (shift, 16, int64_t, <<)
> +DEF_OP_VV (shift, 32, int64_t, <<)
> +DEF_OP_VV (shift, 64, int64_t, <<)
> +DEF_OP_VV (shift, 128, int64_t, <<)
> +DEF_OP_VV (shift, 256, int64_t, <<)
> +DEF_OP_VV (shift, 512, int64_t, <<)
> +
> +/* { dg-final { scan-assembler-times
> {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */
> +/* TODO: Ideally, we should make sure there is no "csrr vlenb". However,
> we still have 'csrr vlenb' for some cases since we don't support VLS mode
> conversion which are needed by division. */
> +/* { dg-final { scan-assembler-times {csrr} 18 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
> new file mode 100644
> index 00000000000..56b6ef92c83
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
> @@ -0,0 +1,57 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
> +
> +#include "def.h"
> +
> +DEF_OP_VI_7 (shift, 1, int8_t, >>)
> +DEF_OP_VI_7 (shift, 2, int8_t, >>)
> +DEF_OP_VI_7 (shift, 4, int8_t, >>)
> +DEF_OP_VI_7 (shift, 8, int8_t, >>)
> +DEF_OP_VI_7 (shift, 16, int8_t, >>)
> +DEF_OP_VI_7 (shift, 32, int8_t, >>)
> +DEF_OP_VI_7 (shift, 64, int8_t, >>)
> +DEF_OP_VI_7 (shift, 128, int8_t, >>)
> +DEF_OP_VI_7 (shift, 256, int8_t, >>)
> +DEF_OP_VI_7 (shift, 512, int8_t, >>)
> +DEF_OP_VI_7 (shift, 1024, int8_t, >>)
> +DEF_OP_VI_7 (shift, 2048, int8_t, >>)
> +DEF_OP_VI_7 (shift, 4096, int8_t, >>)
> +
> +DEF_OP_VI_7 (shift, 1, int16_t, >>)
> +DEF_OP_VI_7 (shift, 2, int16_t, >>)
> +DEF_OP_VI_7 (shift, 4, int16_t, >>)
> +DEF_OP_VI_7 (shift, 8, int16_t, >>)
> +DEF_OP_VI_7 (shift, 16, int16_t, >>)
> +DEF_OP_VI_7 (shift, 32, int16_t, >>)
> +DEF_OP_VI_7 (shift, 64, int16_t, >>)
> +DEF_OP_VI_7 (shift, 128, int16_t, >>)
> +DEF_OP_VI_7 (shift, 256, int16_t, >>)
> +DEF_OP_VI_7 (shift, 512, int16_t, >>)
> +DEF_OP_VI_7 (shift, 1024, int16_t, >>)
> +DEF_OP_VI_7 (shift, 2048, int16_t, >>)
> +
> +DEF_OP_VI_7 (shift, 1, int32_t, >>)
> +DEF_OP_VI_7 (shift, 2, int32_t, >>)
> +DEF_OP_VI_7 (shift, 4, int32_t, >>)
> +DEF_OP_VI_7 (shift, 8, int32_t, >>)
> +DEF_OP_VI_7 (shift, 16, int32_t, >>)
> +DEF_OP_VI_7 (shift, 32, int32_t, >>)
> +DEF_OP_VI_7 (shift, 64, int32_t, >>)
> +DEF_OP_VI_7 (shift, 128, int32_t, >>)
> +DEF_OP_VI_7 (shift, 256, int32_t, >>)
> +DEF_OP_VI_7 (shift, 512, int32_t, >>)
> +DEF_OP_VI_7 (shift, 1024, int32_t, >>)
> +
> +DEF_OP_VI_7 (shift, 1, int64_t, >>)
> +DEF_OP_VI_7 (shift, 2, int64_t, >>)
> +DEF_OP_VI_7 (shift, 4, int64_t, >>)
> +DEF_OP_VI_7 (shift, 8, int64_t, >>)
> +DEF_OP_VI_7 (shift, 16, int64_t, >>)
> +DEF_OP_VI_7 (shift, 32, int64_t, >>)
> +DEF_OP_VI_7 (shift, 64, int64_t, >>)
> +DEF_OP_VI_7 (shift, 128, int64_t, >>)
> +DEF_OP_VI_7 (shift, 256, int64_t, >>)
> +DEF_OP_VI_7 (shift, 512, int64_t, >>)
> +
> +/* { dg-final { scan-assembler-times {vsra\.vi\s+v[0-9]+,\s*v[0-9]+,\s*7}
> 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
> new file mode 100644
> index 00000000000..c909cb1a75a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
> @@ -0,0 +1,57 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
> +
> +#include "def.h"
> +
> +DEF_OP_VI_7 (shift, 1, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 2, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 4, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 8, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 16, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 32, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 64, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 128, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 256, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 512, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 1024, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 2048, uint8_t, >>)
> +DEF_OP_VI_7 (shift, 4096, uint8_t, >>)
> +
> +DEF_OP_VI_7 (shift, 1, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 2, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 4, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 8, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 16, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 32, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 64, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 128, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 256, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 512, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 1024, uint16_t, >>)
> +DEF_OP_VI_7 (shift, 2048, uint16_t, >>)
> +
> +DEF_OP_VI_7 (shift, 1, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 2, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 4, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 8, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 16, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 32, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 64, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 128, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 256, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 512, uint32_t, >>)
> +DEF_OP_VI_7 (shift, 1024, uint32_t, >>)
> +
> +DEF_OP_VI_7 (shift, 1, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 2, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 4, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 8, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 16, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 32, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 64, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 128, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 256, uint64_t, >>)
> +DEF_OP_VI_7 (shift, 512, uint64_t, >>)
> +
> +/* { dg-final { scan-assembler-times {vsrl\.vi\s+v[0-9]+,\s*v[0-9]+,\s*7}
> 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
> new file mode 100644
> index 00000000000..fdea84c39d8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
> @@ -0,0 +1,57 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
> +
> +#include "def.h"
> +
> +DEF_OP_VI_7 (shift, 1, int8_t, <<)
> +DEF_OP_VI_7 (shift, 2, int8_t, <<)
> +DEF_OP_VI_7 (shift, 4, int8_t, <<)
> +DEF_OP_VI_7 (shift, 8, int8_t, <<)
> +DEF_OP_VI_7 (shift, 16, int8_t, <<)
> +DEF_OP_VI_7 (shift, 32, int8_t, <<)
> +DEF_OP_VI_7 (shift, 64, int8_t, <<)
> +DEF_OP_VI_7 (shift, 128, int8_t, <<)
> +DEF_OP_VI_7 (shift, 256, int8_t, <<)
> +DEF_OP_VI_7 (shift, 512, int8_t, <<)
> +DEF_OP_VI_7 (shift, 1024, int8_t, <<)
> +DEF_OP_VI_7 (shift, 2048, int8_t, <<)
> +DEF_OP_VI_7 (shift, 4096, int8_t, <<)
> +
> +DEF_OP_VI_7 (shift, 1, int16_t, <<)
> +DEF_OP_VI_7 (shift, 2, int16_t, <<)
> +DEF_OP_VI_7 (shift, 4, int16_t, <<)
> +DEF_OP_VI_7 (shift, 8, int16_t, <<)
> +DEF_OP_VI_7 (shift, 16, int16_t, <<)
> +DEF_OP_VI_7 (shift, 32, int16_t, <<)
> +DEF_OP_VI_7 (shift, 64, int16_t, <<)
> +DEF_OP_VI_7 (shift, 128, int16_t, <<)
> +DEF_OP_VI_7 (shift, 256, int16_t, <<)
> +DEF_OP_VI_7 (shift, 512, int16_t, <<)
> +DEF_OP_VI_7 (shift, 1024, int16_t, <<)
> +DEF_OP_VI_7 (shift, 2048, int16_t, <<)
> +
> +DEF_OP_VI_7 (shift, 1, int32_t, <<)
> +DEF_OP_VI_7 (shift, 2, int32_t, <<)
> +DEF_OP_VI_7 (shift, 4, int32_t, <<)
> +DEF_OP_VI_7 (shift, 8, int32_t, <<)
> +DEF_OP_VI_7 (shift, 16, int32_t, <<)
> +DEF_OP_VI_7 (shift, 32, int32_t, <<)
> +DEF_OP_VI_7 (shift, 64, int32_t, <<)
> +DEF_OP_VI_7 (shift, 128, int32_t, <<)
> +DEF_OP_VI_7 (shift, 256, int32_t, <<)
> +DEF_OP_VI_7 (shift, 512, int32_t, <<)
> +DEF_OP_VI_7 (shift, 1024, int32_t, <<)
> +
> +DEF_OP_VI_7 (shift, 1, int64_t, <<)
> +DEF_OP_VI_7 (shift, 2, int64_t, <<)
> +DEF_OP_VI_7 (shift, 4, int64_t, <<)
> +DEF_OP_VI_7 (shift, 8, int64_t, <<)
> +DEF_OP_VI_7 (shift, 16, int64_t, <<)
> +DEF_OP_VI_7 (shift, 32, int64_t, <<)
> +DEF_OP_VI_7 (shift, 64, int64_t, <<)
> +DEF_OP_VI_7 (shift, 128, int64_t, <<)
> +DEF_OP_VI_7 (shift, 256, int64_t, <<)
> +DEF_OP_VI_7 (shift, 512, int64_t, <<)
> +
> +/* { dg-final { scan-assembler-times {vsll\.vi\s+v[0-9]+,\s*v[0-9]+,\s*7}
> 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> --
> 2.36.1
>
>
next prev parent reply other threads:[~2023-08-08 2:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-08 1:37 Juzhe-Zhong
2023-08-08 2:18 ` Kito Cheng [this message]
2023-08-08 2:31 ` Lehua Ding
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