From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92f.google.com (mail-ua1-x92f.google.com [IPv6:2607:f8b0:4864:20::92f]) by sourceware.org (Postfix) with ESMTPS id DB64A3858C36 for ; Sun, 5 Mar 2023 10:19:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DB64A3858C36 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x92f.google.com with SMTP id d12so4502372uak.10 for ; Sun, 05 Mar 2023 02:19:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678011540; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ItpCsjFUP2xOk3oNqAAoIyf0v2TMH27upAbD5gYRwPM=; b=LOqGXbgjLsG5q1dHLl9zHT85iqay7A79k7/+q5sOCL4UT/uqx8cr9yD7sifGkTB0l5 YqW4mTdO6dP6yuaxZbJpLlZANs006PY7MCZLXqsmgKPCMin5OPy2V/L/ScQS8obGP3E1 RETbBpu9Bp9ZAYQt2rReiDQKluOhbh/2tB6XX2qBo/nHvk/cAgMDm72ckAjwHOl3hr+R /1D5Y2AjPVv6Cb4+2cGyo7v8j0PBzISk+lu77DAHz3NvrNCINr6kheKQ0n+0sUYBoTX0 SBpTbhjj33YXNehq4ClJQc7/6tilsK29+Wq1XZ/n6adc+J4CYdhutcYsJLDMpTfC+USz qGUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678011540; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ItpCsjFUP2xOk3oNqAAoIyf0v2TMH27upAbD5gYRwPM=; b=28Hk7UI1DjxXWKUbvb3DMg+ugqRH3jnVv5nHX1+aoy56JYLKHnD9uKNwdCIw0VC1Z+ bNibFXUhUkjNGJMiSZD5PhK7vbSBYIZIWW2eRbn0RNRn3Vwu4rpD1Ep2f/4mY8JG7vjy GLCARP/jfvCqHJVhNfw37UDEgDXTcZ0fcykt1xmkBHhIPf3qE7p1vNgNHN/EUngde+Qk sKLEgttjSCEmikwmproj9k0Ohks6+cfXfm0uOUl+n17PGbujLeRyEpYTri0ZWQ3AFGyV ytl+gtskFKB0ukUKV7bpTad5bHrq2P7WBBUfv2qK0P+uqafSyU730PcgxzHbKBhb8fqj RbZQ== X-Gm-Message-State: AO0yUKVNhQMbphIgYG6Lbon5sQQbkWDDBHuDKnXrLsCUJCVCGoOEJdfI k3V2QWYzxjuwZDMT8X+rI4mNcxyVjf/Hdq4fmrc= X-Google-Smtp-Source: AK7set/nMZZ4ECvsTQrnfcOVnXwJgP5+lxJ4u8jwo0CSzu/RQDOytt6FppfMf8G3BY5ve0hagN8NpnBYyVajcjJY7T4= X-Received: by 2002:a1f:2048:0:b0:406:8403:4e64 with SMTP id g69-20020a1f2048000000b0040684034e64mr4698232vkg.2.1678011539994; Sun, 05 Mar 2023 02:18:59 -0800 (PST) MIME-Version: 1.0 References: <20230302083534.4076244-1-christoph.muellner@vrull.eu> In-Reply-To: <20230302083534.4076244-1-christoph.muellner@vrull.eu> From: Kito Cheng Date: Sun, 5 Mar 2023 18:18:48 +0800 Message-ID: Subject: Re: [PATCH v4 0/9] RISC-V: Add XThead* extension support To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu , Andrew Pinski , Hans-Peter Nilsson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM :) On Thu, Mar 2, 2023 at 4:36=E2=80=AFPM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This series introduces support for the T-Head specific RISC-V ISA extensi= ons > which are available e.g. on the T-Head XuanTie C906. > > The ISA spec can be found here: > https://github.com/T-head-Semi/thead-extension-spec > > This series adds support for the following XThead* extensions: > * XTheadBa > * XTheadBb > * XTheadBs > * XTheadCmo > * XTheadCondMov > * XTheadFmv > * XTheadInt > * XTheadMac > * XTheadMemPair > * XTheadSync > > All extensions are properly integrated and the included tests > demonstrate the improvements of the generated code. > > The series also introduces support for "-mcpu=3Dthead-c906", which also > enables all available XThead* ISA extensions of the T-Head C906. > > All patches have been tested and don't introduce regressions for RV32 or = RV64. > The patches have also been tested with SPEC CPU2017 on QEMU and real HW > (D1 board). > > Support patches for these extensions for Binutils, QEMU, and LLVM have > already been merged in the corresponding upstream projects. > > Patches 1-8 from this series (everything except the last one) got an ACK > by Kito. However, since there were a few comments after the ACK, I > decided to send out a v4, so that reviewers can verify that their > comments have been addressed properly. > > Note, that there was a concern raised by Andrew Pinski (on CC), which > might not be resolved with this series (I could not reproduce the issue, > but I might have misunderstood something). > > Changes in v4: > - Drop XTheadMemIdx and XTheadFMemIdx (will be a follow-up series) > - Replace 'immediate_operand' by 'const_int_operand' in many patterns > - Small cleanups in XTheadBb > - Factor out C code into thead.cc (XTheadMemPair) to minimize changes in > riscv.cc > > Changes in v3: > - Bugfix in XTheadBa > - Rewrite of XTheadMemPair > - Inclusion of XTheadMemIdx and XTheadFMemIdx > > Christoph M=C3=BCllner (9): > riscv: Add basic XThead* vendor extension support > riscv: riscv-cores.def: Add T-Head XuanTie C906 > riscv: thead: Add support for the XTheadBa ISA extension > riscv: thead: Add support for the XTheadBs ISA extension > riscv: thead: Add support for the XTheadBb ISA extension > riscv: thead: Add support for the XTheadCondMov ISA extensions > riscv: thead: Add support for the XTheadMac ISA extension > riscv: thead: Add support for the XTheadFmv ISA extension > riscv: thead: Add support for the XTheadMemPair ISA extension > > gcc/common/config/riscv/riscv-common.cc | 26 ++ > gcc/config.gcc | 1 + > gcc/config/riscv/bitmanip.md | 52 ++- > gcc/config/riscv/constraints.md | 8 + > gcc/config/riscv/iterators.md | 4 + > gcc/config/riscv/peephole.md | 56 +++ > gcc/config/riscv/riscv-cores.def | 4 + > gcc/config/riscv/riscv-opts.h | 26 ++ > gcc/config/riscv/riscv-protos.h | 16 +- > gcc/config/riscv/riscv.cc | 226 +++++++-- > gcc/config/riscv/riscv.md | 67 ++- > gcc/config/riscv/riscv.opt | 3 + > gcc/config/riscv/t-riscv | 4 + > gcc/config/riscv/thead.cc | 427 ++++++++++++++++++ > gcc/config/riscv/thead.md | 346 ++++++++++++++ > .../gcc.target/riscv/mcpu-thead-c906.c | 28 ++ > .../gcc.target/riscv/xtheadba-addsl.c | 55 +++ > gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + > .../gcc.target/riscv/xtheadbb-extu-2.c | 22 + > .../gcc.target/riscv/xtheadbb-extu.c | 22 + > gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + > gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 ++ > .../gcc.target/riscv/xtheadbb-srri.c | 25 + > gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + > gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + > .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 ++ > .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 ++ > .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 ++ > .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 ++ > .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 ++ > .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 ++ > .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 ++ > .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 ++ > .../gcc.target/riscv/xtheadcondmov.c | 14 + > .../gcc.target/riscv/xtheadfmemidx.c | 14 + > .../gcc.target/riscv/xtheadfmv-fmv.c | 24 + > gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + > .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 ++ > gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + > .../gcc.target/riscv/xtheadmempair-1.c | 98 ++++ > .../gcc.target/riscv/xtheadmempair-2.c | 84 ++++ > .../gcc.target/riscv/xtheadmempair-3.c | 29 ++ > .../gcc.target/riscv/xtheadmempair.c | 13 + > gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + > 49 files changed, 2196 insertions(+), 67 deletions(-) > create mode 100644 gcc/config/riscv/thead.cc > create mode 100644 gcc/config/riscv/thead.md > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-im= m-eqz.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-im= m-not.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-re= g-eqz.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-re= g-not.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-im= m-cond.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-im= m-nez.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-re= g-cond.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-re= g-nez.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c > > -- > 2.39.2 >