From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x933.google.com (mail-ua1-x933.google.com [IPv6:2607:f8b0:4864:20::933]) by sourceware.org (Postfix) with ESMTPS id B32733858D20 for ; Thu, 10 Nov 2022 01:24:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B32733858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x933.google.com with SMTP id y25so113963ual.2 for ; Wed, 09 Nov 2022 17:24:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=y0rI3TMS7aYulwfDD/uQhl8e0yy6dTFtHsWbgjLRFjk=; b=kkBm07h4Dtvj0NsY42LXjozqzv69b5AY34XPogxdqsiNT7EH70dT02vfXHknoU+Tzu GmjgeTnQpyLtmIJ1lJdfAe+DXd+6bJUpUQCCskTPq1s8g+HpfZnnWxjIklbetZ/RhOse Nx3dpcGJQDAY+qFX3lELMWM7UuU+EiQp78odvW4j/I5wB4h4shTLT34cnxYhmYX6rIMj ksjA9SOWyjIbZg1qyH9NRbwLUZzv6T1upvs5NZu8zlTA76i+qF0rMz+5ca2FOT3ARiwE WThth8n7D+0+v3/Ew5/dK8NvnV+3hc0OB/EaQXJ3K6D9rkEFPZ5j5dkFLU713P5Ehjoe 8Cmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=y0rI3TMS7aYulwfDD/uQhl8e0yy6dTFtHsWbgjLRFjk=; b=VGAimmup8LKoM6DwQBzWePRr5Oqa2LeDxQfDOOJ8Oybppjn6qNUiNX85/fsT8jmfa4 xZCvhAVSEhENR6S86bZVX9xlA7eh9UkNMa6VlLxtQ2x1wbsUf7eS+sDKH6q/JuBD3n3Y E3V/uUbcA4/pmK4l2MGlvwSqD+ey2bn1uvO5awNzAJ2w6Vy8S6qELNEhXsW+D57wSILn SMtPU73ODmFFyfB6l58NMmtgJQolCsy6mQV2yC4KgU+vgBYs43BoxBSM1SG9HeMLFiIr RwfzSD4x3t7fjG1ERL+mcPXvC0WMFsOL77aJBrU0mshFrNfOppWcKaQDlJWo1Casp0Es jfHg== X-Gm-Message-State: ACrzQf2Wnhlg4lNVMnyX5jmraUcwmjzCiHFR6VKqWCilxRCyeTKR3ymT Gskkqm8NPYzxieerCrixn2z+SMTVfL1ZKTLHurY= X-Google-Smtp-Source: AMsMyM5pf2GNOPulKdD/qQhwgfnZzO1bT251SnngZNW4/n0SkGHAnditTKxzFt73ZR3zLRZTKvvp7s5Az7sQ8ar4hKM= X-Received: by 2002:ab0:132d:0:b0:3de:4c7d:2b08 with SMTP id g42-20020ab0132d000000b003de4c7d2b08mr20328848uae.32.1668043498834; Wed, 09 Nov 2022 17:24:58 -0800 (PST) MIME-Version: 1.0 References: <20221109230736.3240512-1-philipp.tomsich@vrull.eu> In-Reply-To: <20221109230736.3240512-1-philipp.tomsich@vrull.eu> From: Kito Cheng Date: Wed, 9 Nov 2022 17:24:47 -0800 Message-ID: Subject: Re: [PATCH] RISC-V: Implement movmisalign to enable SLP To: Philipp Tomsich Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , Jeff Law , Palmer Dabbelt , Christoph Muellner Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I am not sure if I am missing something, your testcase should rely on movmisalignhi pattern, but you defined movmisalign with ANYF mode iterator rather than movmisalign with HI, SI, DI? And seems the testcase compile with `-march=rv64gc -mabi=lp64 -mtune=size -O2` w/o this patch already generated lhu/sh pair? On Wed, Nov 9, 2022 at 3:08 PM Philipp Tomsich wrote: > > The default implementation of support_vector_misalignment() checks > whether movmisalign is present for the requested mode. This > will be used by vect_supportable_dr_alignment() to determine whether a > misaligned access of vectorized data is permissible. > > For RISC-V this is required to convert multiple integer data refs, > such as "c[1] << 8) | c[0]" into a larger (in the example before: a > halfword load) access. > We conditionalize on !riscv_slow_unaligned_access_p to allow the > misaligned refs, if they are not expected to be slow. > > This benefits both xalancbmk and blender on SPEC CPU 2017. > > gcc/ChangeLog: > > * config/riscv/riscv.md (movmisalign): Implement. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/movmisalign-1.c: New test. > * gcc.target/riscv/movmisalign-2.c: New test. > * gcc.target/riscv/movmisalign-3.c: New test. > > Signed-off-by: Philipp Tomsich > --- > > gcc/config/riscv/riscv.md | 18 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++ > gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++ > gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++ > 4 files changed, 54 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-3.c > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 289ff7470c6..1b357a9c57f 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -1715,6 +1715,24 @@ > MAX_MACHINE_MODE, &operands[3], TRUE); > }) > > +;; Misaligned (integer) moves: provide an implementation for > +;; movmisalign, so the default support_vector_misalignment() will > +;; return the right boolean depending on whether > +;; riscv_slow_unaligned_access_p is set or not. > +;; > +;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a > +;; HImode load (a good test case will be blender and xalancbmk in SPEC > +;; CPU 2017). > +;; > +(define_expand "movmisalign" > + [(set (match_operand:ANYI 0 "") > + (match_operand:ANYI 1 ""))] > + "!riscv_slow_unaligned_access_p" > +{ > + if (riscv_legitimize_move (mode, operands[0], operands[1])) > + DONE; > +}) > + > ;; 64-bit integer moves > > (define_expand "movdi" > diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c > new file mode 100644 > index 00000000000..791a3d63335 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c > @@ -0,0 +1,12 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > + > +void f(unsigned short *sink, unsigned char *arr) > +{ > + *sink = (arr[1] << 8) | arr[0]; > +} > + > +/* { dg-final { scan-assembler-times "lhu\t" 1 } } */ > +/* { dg-final { scan-assembler-not "lbu\t" } } */ > + > diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c > new file mode 100644 > index 00000000000..ef73dcb2d9d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c > @@ -0,0 +1,12 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > + > +void f(unsigned short *sink, unsigned char *arr) > +{ > + *sink = (arr[1] << 8) | arr[0]; > +} > + > +/* { dg-final { scan-assembler-times "lbu\t" 2 } } */ > +/* { dg-final { scan-assembler-not "lhu\t" } } */ > + > diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c > new file mode 100644 > index 00000000000..963b11c27fd > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c > @@ -0,0 +1,12 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > + > +void f(unsigned short *sink, unsigned char *arr) > +{ > + *sink = (arr[1] << 8) | arr[0]; > +} > + > +/* { dg-final { scan-assembler-times "lbu\t" 2 } } */ > +/* { dg-final { scan-assembler-not "lhu\t" } } */ > + > -- > 2.34.1 >