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From: Kito Cheng <kito.cheng@gmail.com>
To: "Li, Pan2" <pan2.li@intel.com>
Cc: "GCC Patches" <gcc-patches@gcc.gnu.org>,
	钟居哲 <juzhe.zhong@rivai.ai>,
	"yanzhang.wang" <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic.
Date: Thu, 27 Jul 2023 18:49:54 +0800	[thread overview]
Message-ID: <CA+yXCZByC+EWLu+xoiKDsXt8ks_HkKT_ew3wXPGtFxvhPrOm4A@mail.gmail.com> (raw)
In-Reply-To: <20230727104353.3890397-1-pan2.li@intel.com>

[-- Attachment #1: Type: text/plain, Size: 2657 bytes --]

Ok, thanks:)

Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> 於 2023年7月27日 週四 18:45 寫道:

> From: Pan Li <pan2.li@intel.com>
>
> According to below RVV doc, the related intrinsic is not longer needed.
>
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv_vector.h (enum RVV_CSR): Removed.
>         (vread_csr): Ditto.
>         (vwrite_csr): Ditto.
> ---
>  gcc/config/riscv/riscv_vector.h | 51 ---------------------------------
>  1 file changed, 51 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv_vector.h
> b/gcc/config/riscv/riscv_vector.h
> index ff54b6be863..3366fd972b5 100644
> --- a/gcc/config/riscv/riscv_vector.h
> +++ b/gcc/config/riscv/riscv_vector.h
> @@ -35,57 +35,6 @@
>  extern "C" {
>  #endif
>
> -enum RVV_CSR {
> -  RVV_VSTART = 0,
> -  RVV_VXSAT,
> -  RVV_VXRM,
> -  RVV_VCSR,
> -};
> -
> -__extension__ extern __inline unsigned long
> -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> -vread_csr(enum RVV_CSR csr)
> -{
> -  unsigned long rv = 0;
> -  switch (csr)
> -    {
> -    case RVV_VSTART:
> -      __asm__ __volatile__ ("csrr\t%0,vstart" : "=r"(rv) : : "memory");
> -      break;
> -    case RVV_VXSAT:
> -      __asm__ __volatile__ ("csrr\t%0,vxsat" : "=r"(rv) : : "memory");
> -      break;
> -    case RVV_VXRM:
> -      __asm__ __volatile__ ("csrr\t%0,vxrm" : "=r"(rv) : : "memory");
> -      break;
> -    case RVV_VCSR:
> -      __asm__ __volatile__ ("csrr\t%0,vcsr" : "=r"(rv) : : "memory");
> -      break;
> -    }
> -  return rv;
> -}
> -
> -__extension__ extern __inline void
> -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> -vwrite_csr(enum RVV_CSR csr, unsigned long value)
> -{
> -  switch (csr)
> -    {
> -    case RVV_VSTART:
> -      __asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) :
> "memory");
> -      break;
> -    case RVV_VXSAT:
> -      __asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory");
> -      break;
> -    case RVV_VXRM:
> -      __asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory");
> -      break;
> -    case RVV_VCSR:
> -      __asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory");
> -      break;
> -    }
> -}
> -
>  /* NOTE: This implementation of riscv_vector.h is intentionally short.
> It does
>     not define the RVV types and intrinsic functions directly in C and C++
>     code, but instead uses the following pragma to tell GCC to insert the
> --
> 2.34.1
>
>

  reply	other threads:[~2023-07-27 10:50 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-27 10:43 pan2.li
2023-07-27 10:49 ` Kito Cheng [this message]
2023-07-27 12:05   ` Li, Pan2

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