From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x936.google.com (mail-ua1-x936.google.com [IPv6:2607:f8b0:4864:20::936]) by sourceware.org (Postfix) with ESMTPS id 924A03858C2F for ; Thu, 27 Jul 2023 10:50:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 924A03858C2F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x936.google.com with SMTP id a1e0cc1a2514c-794cddcab71so383332241.1 for ; Thu, 27 Jul 2023 03:50:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690455008; x=1691059808; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Um7wYD2iVZmr/ROEHge1MJC3xFs4rt7aGMk2I5zp3ac=; b=QsVGjDbTYvwOyoIxSx7plO/xm4hWEq9g1dGRIEp8ssFt4KZaXj/aeL1i6yf7YwwPez FnxBeTn6Nxzm5mo2CruMWLlZ1NVMyA5EHjUKtwmJH/ZoNvp+LP7OzZuOLYxXmL4tH0RA qXhneqjcSAU8tbXwMLcpp/4H9ZmC85KmI2gsNHHvYcfbCAEbfgUZYMzGbbF3Ap77OgBb FJ2859/NEIrotSXxj4e3qx299mOwAM2o1bfvh//SpgCzO55sJCPSTtxA6hBJbzEbheP1 xjMQUtO+nhIsQ5SQoU1Zc1AmE/rLJMPumYKA4gv247rWIgLLRDQ2QeThDrHclok7J6c8 9V/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690455008; x=1691059808; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Um7wYD2iVZmr/ROEHge1MJC3xFs4rt7aGMk2I5zp3ac=; b=H1yIP9RO7MmAHD0kaKOG8P7hUsiws9ShUzi75GNISAolsJ9yCnNQqRQ0EljswJoUmL hD9hkhIzCtLOJt9cu8eJXq4xjpy8I4DqIxy8Li23pqujkgozqH+RZ2xWnZK28PZShzsZ Dd4wIdeyox6e0iPJnkB65wt1CprA1nSco0iT+BPDAuCXb+/RdhlMfpt8KO8xQqDjo7D5 GXjDbTDyQmc7/9O0aBcV0fMVGkY4WHSuk3GbSn0R4ZYomw3Pp8NlmthY1afN5Ea2B826 eH34Cks92H2+2cecxUNh3uRuNJ3nFsN49aeoOXZuJiU94YZSieoKLhfGL+NgvD2BTmoj qzZA== X-Gm-Message-State: ABy/qLZg4D0HXAE6Xs874k30DBPbUlUgXRZZyh1rPIPu+gsEy9a//lFY UuByDVCAvSdEPxu0LL95oCxYj1pMV4ry1RAv5r8= X-Google-Smtp-Source: APBJJlGlZsxbZ9B/ej2YwI0v7iWwqUrsGy0SAXkG4DXwRB/Sxdw3bQibxGx4J4VfURklkBmWnF5ySMVbHSXFyZg0beA= X-Received: by 2002:a1f:4391:0:b0:47e:f85:7ebc with SMTP id q139-20020a1f4391000000b0047e0f857ebcmr1012086vka.8.1690455007763; Thu, 27 Jul 2023 03:50:07 -0700 (PDT) MIME-Version: 1.0 References: <20230727104353.3890397-1-pan2.li@intel.com> In-Reply-To: <20230727104353.3890397-1-pan2.li@intel.com> From: Kito Cheng Date: Thu, 27 Jul 2023 18:49:54 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic. To: "Li, Pan2" Cc: GCC Patches , =?UTF-8?B?6ZKf5bGF5ZOy?= , "yanzhang.wang" Content-Type: multipart/alternative; boundary="0000000000003f2018060175ba10" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000003f2018060175ba10 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ok, thanks:) Pan Li via Gcc-patches =E6=96=BC 2023=E5=B9=B47= =E6=9C=8827=E6=97=A5 =E9=80=B1=E5=9B=9B 18:45 =E5=AF=AB=E9=81=93=EF=BC=9A > From: Pan Li > > According to below RVV doc, the related intrinsic is not longer needed. > > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249 > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv_vector.h (enum RVV_CSR): Removed. > (vread_csr): Ditto. > (vwrite_csr): Ditto. > --- > gcc/config/riscv/riscv_vector.h | 51 --------------------------------- > 1 file changed, 51 deletions(-) > > diff --git a/gcc/config/riscv/riscv_vector.h > b/gcc/config/riscv/riscv_vector.h > index ff54b6be863..3366fd972b5 100644 > --- a/gcc/config/riscv/riscv_vector.h > +++ b/gcc/config/riscv/riscv_vector.h > @@ -35,57 +35,6 @@ > extern "C" { > #endif > > -enum RVV_CSR { > - RVV_VSTART =3D 0, > - RVV_VXSAT, > - RVV_VXRM, > - RVV_VCSR, > -}; > - > -__extension__ extern __inline unsigned long > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -vread_csr(enum RVV_CSR csr) > -{ > - unsigned long rv =3D 0; > - switch (csr) > - { > - case RVV_VSTART: > - __asm__ __volatile__ ("csrr\t%0,vstart" : "=3Dr"(rv) : : "memory"); > - break; > - case RVV_VXSAT: > - __asm__ __volatile__ ("csrr\t%0,vxsat" : "=3Dr"(rv) : : "memory"); > - break; > - case RVV_VXRM: > - __asm__ __volatile__ ("csrr\t%0,vxrm" : "=3Dr"(rv) : : "memory"); > - break; > - case RVV_VCSR: > - __asm__ __volatile__ ("csrr\t%0,vcsr" : "=3Dr"(rv) : : "memory"); > - break; > - } > - return rv; > -} > - > -__extension__ extern __inline void > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -vwrite_csr(enum RVV_CSR csr, unsigned long value) > -{ > - switch (csr) > - { > - case RVV_VSTART: > - __asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) : > "memory"); > - break; > - case RVV_VXSAT: > - __asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory"= ); > - break; > - case RVV_VXRM: > - __asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory"); > - break; > - case RVV_VCSR: > - __asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory"); > - break; > - } > -} > - > /* NOTE: This implementation of riscv_vector.h is intentionally short. > It does > not define the RVV types and intrinsic functions directly in C and C++ > code, but instead uses the following pragma to tell GCC to insert the > -- > 2.34.1 > > --0000000000003f2018060175ba10--