Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

[Kito Cheng <kito.cheng@gmail.com>]

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Ok for gcc 13 but just wait one more week to make sure everything is fine
as gcc convention :)

Li Xu <xuli1@eswincomputing.com>於 2023年10月24日 週二，15:49寫道：

> Committed to trunk. Thanks juzhe.
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> Li Xu
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> >Ok for trunk (You can commit it to the trunk now).
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> >
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> >For GCC-13,  I'd like to wait for kito's comment.
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> >Thanks.
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> >juzhe.zhong@rivai.ai
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> >From: Li Xu
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> >Date: 2023-10-24 15:29
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> >To: gcc-patches
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> >CC: kito.cheng; palmer; juzhe.zhong
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> >Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
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> >Calling vget/vset intrinsic without receiving a return value will cause
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> >a crash. Because in this case e.target is null.
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> >This patch should be backported to releases/gcc-13.
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> >        PR/target 111935
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> >gcc/ChangeLog:
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> >        * config/riscv/riscv-vector-builtins-bases.cc: fix bug.
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> >gcc/testsuite/ChangeLog:
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> >        * gcc.target/riscv/rvv/base/pr111935.c: New test.
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> >---
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> > .../riscv/riscv-vector-builtins-bases.cc      |  4 +++
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> > .../gcc.target/riscv/rvv/base/pr111935.c      | 26 +++++++++++++++++++
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> > 2 files changed, 30 insertions(+)
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> > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
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> >
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> >diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
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> >index ab12e130907..0b1409a52e0 100644
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> >--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
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> >+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
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> >@@ -1740,6 +1740,8 @@ public:
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> >   rtx expand (function_expander &e) const override
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> >   {
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> >+    if (!e.target)
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> >+      return NULL_RTX;
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> >     rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0));
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> >     gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest)));
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> >     rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
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> >@@ -1777,6 +1779,8 @@ public:
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> >   rtx expand (function_expander &e) const override
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> >   {
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> >+    if (!e.target)
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> >+      return NULL_RTX;
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> >     rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
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> >     gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
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> >     rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
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> >diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
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> >new file mode 100644
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> >index 00000000000..0b936d849a1
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> >--- /dev/null
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> >+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
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> >@@ -0,0 +1,26 @@
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> >+/* { dg-do compile } */
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> >+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */
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> >+
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> >+#include "riscv_vector.h"
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> >+
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> >+inline vuint32m4_t __attribute__((__always_inline__))
> transpose_indexes() {
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> >+  static const uint32_t idx_[16] = {0, 4, 8, 12,
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> >+                      1, 5, 9, 13,
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> >+                      2, 6, 10, 14,
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> >+                      3, 7, 11, 15};
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> >+  return __riscv_vle32_v_u32m4(idx_, 16);
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> >+}
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> >+
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> >+void pffft_real_preprocess_4x4(const float *in) {
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> >+  vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4);
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> >+  vfloat32m4_t tmp = __riscv_vundefined_f32m4();
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> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0);
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> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0);
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> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0);
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> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0);
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> >+  tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
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> >+  r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
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> >+}
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> >+
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> >+/* { dg-final { scan-assembler-times
> {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 10 } } */
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> >+/* { dg-final { scan-assembler-times
> {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 8 } } */
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> >--
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> >2.17.1
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> >
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> >
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> >xuli1@eswincomputing.com
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