From: Kito Cheng <kito.cheng@gmail.com>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
rguenther <rguenther@suse.de>,
gcc-patches <gcc-patches@gcc.gnu.org>,
"richard.sandiford" <richard.sandiford@arm.com>,
apinski <apinski@marvell.com>
Subject: Re: [PATCH] CPROP: Allow cprop optimization when the function has a single block
Date: Thu, 2 Feb 2023 23:18:59 +0800 [thread overview]
Message-ID: <CA+yXCZC-fB+mGBuS6Oe=-5=p6=38aph2tYreFg7-_5UcGLV2Nw@mail.gmail.com> (raw)
In-Reply-To: <b0b43224-f10a-b522-6c8d-9edb8f493b68@gmail.com>
> > Thank you so much. Kito helped me fix it already.
> > RVV instruction patterns can have CSE optimizations now.
> What was the issue?
VL and VTYPE isn't listed in fixed register so CSE feel that isn't
cheap (See CHEAP_REGNO in cse.cc),
but actually it's kind of mistake sett for VL and VTYPE register to
non fixed register,
it all managed by vsetvl insertion pass, and won't involved into the
register allocation
process, so it should be set 1 in FIXED_REGISTERS,
then CSE pass is happy to cse that after we fix that :)
More story behind that is we were trying to rely on RA to manage VL
and VTYPE before,
and then...we gave up and decided to manage that by ourselves.
next prev parent reply other threads:[~2023-02-02 15:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-01 12:24 juzhe.zhong
2023-02-01 12:40 ` Richard Biener
2023-02-01 12:47 ` juzhe.zhong
2023-02-01 12:51 ` Richard Biener
2023-02-01 12:56 ` juzhe.zhong
[not found] ` <0CEDD257-703F-4ED3-B927-C21279557CE6@gmail.com>
2023-02-02 1:49 ` juzhe.zhong
2023-02-02 12:26 ` Richard Biener
2023-02-02 12:35 ` juzhe.zhong
2023-02-02 14:36 ` Jeff Law
2023-02-02 14:43 ` juzhe.zhong
2023-02-02 15:18 ` Kito Cheng [this message]
2023-02-02 14:36 ` Jeff Law
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