From: Kito Cheng <kito.cheng@gmail.com>
To: 钟居哲 <juzhe.zhong@rivai.ai>
Cc: Li Xu <xuli1@eswincomputing.com>,
gcc-patches <gcc-patches@gcc.gnu.org>,
palmer <palmer@dabbelt.com>, "pan2.li" <pan2.li@intel.com>
Subject: Re: [PATCH] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]
Date: Fri, 28 Jul 2023 14:45:52 +0800 [thread overview]
Message-ID: <CA+yXCZC0umh+612Ah4td8D0RfseFGYFKvWPdESMzGsF6RF9w8w@mail.gmail.com> (raw)
In-Reply-To: <D07E0F394D619C19+2023072814422327044682@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 63436 bytes --]
I didn't checked with rvv intrinsic spec, but I assume this is found during
test with api test, so LGTM, thanks for fixing this:)
juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> 於 2023年7月28日 週五 14:43 寫道：
> Thanks for fixing it.
> LGTM from my side.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Li Xu
> Date: 2023-07-28 13:52
> To: gcc-patches
> CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
> Subject: [PATCH] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]
> From: xuli <xuli1@eswincomputing.com>
>
> Computation of `vsadd`, `vsaddu`, `vssub`, and `vssubu` do not need the
> rounding mode, therefore the intrinsics of these instructions do not have
> the parameter for rounding mode control.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc: remove rounding
> mode of vsadd[u] and vssub[u].
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/bug-12.C: Adapt testcase.
> * g++.target/riscv/rvv/base/bug-14.C: Ditto.
> * g++.target/riscv/rvv/base/bug-18.C: Ditto.
> * g++.target/riscv/rvv/base/bug-19.C: Ditto.
> * g++.target/riscv/rvv/base/bug-20.C: Ditto.
> * g++.target/riscv/rvv/base/bug-21.C: Ditto.
> * g++.target/riscv/rvv/base/bug-22.C: Ditto.
> * g++.target/riscv/rvv/base/bug-23.C: Ditto.
> * g++.target/riscv/rvv/base/bug-3.C: Ditto.
> * g++.target/riscv/rvv/base/bug-8.C: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: Ditto.
> * gcc.target/riscv/rvv/base/merge_constraint-1.c: Ditto.
> * gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c: New test.
> * gcc.target/riscv/rvv/base/fixed-point-vxrm.c: New test.
> ---
> .../riscv/riscv-vector-builtins-bases.cc | 6 --
> gcc/config/riscv/vector.md | 42 +++-------
> .../g++.target/riscv/rvv/base/bug-12.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-14.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-18.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-19.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-20.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-21.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-22.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-23.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-3.C | 2 +-
> .../g++.target/riscv/rvv/base/bug-8.C | 2 +-
> .../riscv/rvv/base/binop_vx_constraint-100.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-101.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-102.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-103.c | 28 +++----
> .../riscv/rvv/base/binop_vx_constraint-104.c | 16 ++--
> .../riscv/rvv/base/binop_vx_constraint-105.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-106.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-107.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-108.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-109.c | 28 +++----
> .../riscv/rvv/base/binop_vx_constraint-110.c | 16 ++--
> .../riscv/rvv/base/binop_vx_constraint-111.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-112.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-113.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-114.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-115.c | 16 ++--
> .../riscv/rvv/base/binop_vx_constraint-116.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-117.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-118.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-119.c | 4 +-
> .../riscv/rvv/base/binop_vx_constraint-97.c | 28 +++----
> .../riscv/rvv/base/binop_vx_constraint-98.c | 16 ++--
> .../riscv/rvv/base/fixed-point-vxrm-error.c | 24 ++++++
> .../riscv/rvv/base/fixed-point-vxrm.c | 81 +++++++++++++++++++
> .../riscv/rvv/base/merge_constraint-1.c | 4 +-
> 37 files changed, 233 insertions(+), 152 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 78c259f801b..316b35b57c8 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -260,12 +260,6 @@ template<rtx_code CODE>
> class binop : public function_base
> {
> public:
> - bool has_rounding_mode_operand_p () const override
> - {
> - return CODE == SS_PLUS || CODE == SS_MINUS || CODE == US_PLUS
> - || CODE == US_MINUS;
> - }
> -
> rtx expand (function_expander &e) const override
> {
> switch (e.op_info->op)
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f38cf901a6b..6ebbefc4ff6 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -848,7 +848,7 @@
> ;; Defines rounding mode of an fixed-point operation.
> (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
> - (cond [(eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
> + (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
> (cond
> [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
> (const_string "rnu")
> @@ -3756,10 +3756,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i, i,
> i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i, i,
> i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i, i,
> i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i, i,
> i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (any_sat_int_binop:VI
> (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr,
> vr, vr")
> (match_operand:VI 4 "<binop_rhs2_predicate>"
> "<binop_rhs2_constraint>"))
> @@ -3787,10 +3785,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_plus_binop:VI_QHS
> (vec_duplicate:VI_QHS
> (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
> @@ -3810,10 +3806,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_minus_binop:VI_QHS
> (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
> (vec_duplicate:VI_QHS
> @@ -3833,10 +3827,8 @@
> (match_operand 6 "const_int_operand")
> (match_operand 7 "const_int_operand")
> (match_operand 8 "const_int_operand")
> - (match_operand 9 "const_int_operand")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_plus_binop:VI_D
> (vec_duplicate:VI_D
> (match_operand:<VEL> 4 "reg_or_int_operand"))
> @@ -3853,7 +3845,7 @@
> [] (rtx *operands, rtx boardcast_scalar) {
> emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
> operands[2], operands[3], boardcast_scalar, operands[5],
> - operands[6], operands[7], operands[8], operands[9]));
> + operands[6], operands[7], operands[8]));
> }))
> DONE;
> })
> @@ -3867,10 +3859,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_plus_binop:VI_D
> (vec_duplicate:VI_D
> (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
> @@ -3890,10 +3880,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_plus_binop:VI_D
> (vec_duplicate:VI_D
> (sign_extend:<VEL>
> @@ -3914,10 +3902,8 @@
> (match_operand 6 "const_int_operand")
> (match_operand 7 "const_int_operand")
> (match_operand 8 "const_int_operand")
> - (match_operand 9 "const_int_operand")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_minus_binop:VI_D
> (match_operand:VI_D 3 "register_operand")
> (vec_duplicate:VI_D
> @@ -3934,7 +3920,7 @@
> [] (rtx *operands, rtx boardcast_scalar) {
> emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
> operands[2], operands[3], boardcast_scalar, operands[5],
> - operands[6], operands[7], operands[8], operands[9]));
> + operands[6], operands[7], operands[8]));
> }))
> DONE;
> })
> @@ -3948,10 +3934,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_minus_binop:VI_D
> (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
> (vec_duplicate:VI_D
> @@ -3971,10 +3955,8 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> - (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (sat_int_minus_binop:VI_D
> (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
> (vec_duplicate:VI_D
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
> index ea992327202..8ff69597ab8 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
> @@ -335,7 +335,7 @@ vbool32_t var_14 =
> __riscv_vmseq_vv_u32m1_b32_mu(var_39, var_40, var_41, var_42,
> // 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
> __riscv_vsetvl_e32m8(27);
> -vint32m8_t var_0 = __riscv_vssub_vx_i32m8(var_59, var_1, 0, 27);
> +vint32m8_t var_0 = __riscv_vssub_vx_i32m8(var_59, var_1, 27);
> // -1061068412, -1776580354, -100935733, 1111812123, 840849367,
> 1454689778, -1416961586, 286847306, 2118070565, 1965230406, -1040658036,
> 587048909, 1667471177, -1452995359, 1549864288, 1955648606, -1153689461,
> -105253108, 1792194502, -341148625, 630712685, -1367196047, 1561028022,
> -599776667, 1447136930, -480839967, -1960624419
> __riscv_vsetvl_e32m8(19);
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
> index d833d4d80c5..a9935c131ff 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
> @@ -415,7 +415,7 @@ int32_t var_9 = __riscv_vmv_x_s_i32m4_i32(var_10);
> // 0
> __riscv_vsetvl_e32mf2(2);
> -vint32mf2_t var_2 = __riscv_vsadd_vx_i32mf2_mu(var_47, var_48, var_49,
> var_9, 0, 2);
> +vint32mf2_t var_2 = __riscv_vsadd_vx_i32mf2_mu(var_47, var_48, var_49,
> var_9, 2);
> // 470559939, 1961139923
> __riscv_vsuxei64_v_i32mf2(var_115, var_112, var_2, 2);
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
> index 71dec9f21c8..868ec1ef90f 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
> @@ -121,7 +121,7 @@ asm volatile ("ttt":::"memory");
> if (check(k, ab, aa))
> cerr << "check 8 fails" << endl;
> vbool64_t var_2 = __riscv_vmsne_vx_u32mf2_b64_mu(var_55, var_56, var_3,
> au, 2);
> - vint16mf4_t var_1 = __riscv_vssub_vv_i16mf4_mu(var_2, var_0, var_4, cg,
> 0, 2);
> + vint16mf4_t var_1 = __riscv_vssub_vv_i16mf4_mu(var_2, var_0, var_4, cg,
> 2);
> vint16mf4_t var_5 = __riscv_vxor_vv_i16mf4_mu(var_46, var_1, bw, bx, 2);
> vint32mf2_t var_18 = __riscv_vwmaccsu_vv_i32mf2(bf, var_1, bg, 2);
> vint8mf8_t var_6 = __riscv_vncvt_x_x_w_i8mf8_mu(var_8, var_7, var_5, 1);
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
> index fc5e09b89fc..a6ba9580416 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C
> @@ -131,7 +131,7 @@
> vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58,
> var_0, var_59, 1);
> __riscv_vse64_v_i64m8(var_74, var_3, 2);
> vuint64m8_t var_10 = __riscv_vmadd_vv_u64m8_mu(var_13, var_6, var_51,
> var_52, 13);
> - vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 0, 13);
> + vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 13);
> vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55,
> var_56, 1);
> vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8,
> var_47, var_48, 1);
> if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl;
> return_value = 1;}
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
> index 81d0cd74465..2a8591f1d3e 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C
> @@ -131,7 +131,7 @@
> vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58,
> var_0, var_59, 1);
> __riscv_vse64_v_i64m8(var_74, var_3, 2);
> vuint64m8_t var_10 = __riscv_vmacc_vv_u64m8_mu(var_13, var_6, var_51,
> var_52, 13);
> - vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 0, 13);
> + vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 13);
> vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55,
> var_56, 1);
> vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8,
> var_47, var_48, 1);
> if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl;
> return_value = 1;}
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
> index 5c6e8283c48..77e06bf1f10 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C
> @@ -131,7 +131,7 @@
> vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58,
> var_0, var_59, 1);
> __riscv_vse64_v_i64m8(var_74, var_3, 2);
> vuint64m8_t var_10 = __riscv_vnmsub_vv_u64m8_mu(var_13, var_6, var_51,
> var_52, 13);
> - vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 0, 13);
> + vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 13);
> vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55,
> var_56, 1);
> vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8,
> var_47, var_48, 1);
> if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl;
> return_value = 1;}
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
> index aaacb320e0a..8ba18a02b83 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C
> @@ -131,7 +131,7 @@
> vuint64m1_t var_8 = __riscv_vredand_vs_u64m8_u64m1_tum(var_13, var_58,
> var_0, var_59, 1);
> __riscv_vse64_v_i64m8(var_74, var_3, 2);
> vuint64m8_t var_10 = __riscv_vnmsac_vv_u64m8_mu(var_13, var_6, var_51,
> var_52, 13);
> - vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 0, 13);
> + vuint64m8_t var_15 = __riscv_vssubu_vv_u64m8_mu(var_33, var_6, var_34,
> var_35, 13);
> vuint64m1_t var_9 = __riscv_vadd_vv_u64m1_mu(var_54, var_8, var_55,
> var_56, 1);
> vuint64m1_t var_11 = __riscv_vredxor_vs_u64m4_u64m1_tum(var_46, var_8,
> var_47, var_48, 1);
> if(!check(var_74, var_129, var_130)) {cerr << "check 128 fails" << endl;
> return_value = 1;}
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
> index d750a77bd77..061063bf44d 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C
> @@ -354,7 +354,7 @@ vbool64_t var_63 = __riscv_vmseq_vx_u8mf8_b64(var_69,
> var_70, 2);
> vuint8mf8_t var_19 = __riscv_vsub_vx_u8mf8_tumu(var_20, var_21, var_22,
> var_73, 2);
> // 225, 96
> -vuint32mf2_t var_16 = __riscv_vssubu_vx_u32mf2_tumu(var_33, var_34,
> var_35, var_74, 0, 2);
> +vuint32mf2_t var_16 = __riscv_vssubu_vx_u32mf2_tumu(var_33, var_34,
> var_35, var_74, 2);
> // 3077557042, 4186139873
> __riscv_vsetvl_e64m4(2);
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
> index 1c7e0181f4a..47e31884255 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C
> @@ -309,7 +309,7 @@ __riscv_vsetvl_e32m2(8);
> vbool16_t var_49 = __riscv_vmseq_vv_i32m2_b16(var_50, var_51, 8);
> // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, 0, 0, 0
> -vint16m1_t var_13 = __riscv_vsadd_vx_i16m1(var_0, var_60, 0, 8);
> +vint16m1_t var_13 = __riscv_vsadd_vx_i16m1(var_0, var_60, 8);
> // -9364, 32767, 11538, -10536, 32767, 30906, 30906, 4977
> __riscv_vsetvl_e16m8(7);
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
> index 97459c6b666..7e1d6dbac7c 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C
> @@ -379,7 +379,7 @@ if(!check(var_87, var_122, var_123)) {cerr << "check
> 121 fails" << endl; return_
> vint8m4_t var_5 = __riscv_vnsra_wv_i8m4(var_12, var_48, 43);
> // 0, -2, -5, -7, 0, -3, -1, -1, 0, 0, -5, -90, -1, 0, -15, -1, 0, 0, 0,
> 0, 0, 0, -3, -1, -3, 0, 0, -13, 0, -1, -1, -1, 0, -1, 39, 0, 0, -2, 0, 0,
> -24, -45, 1
> -vint16m8_t var_4 = __riscv_vssub_vx_i16m8_mu(var_6, var_12, var_49,
> var_10, 0, 43);
> +vint16m8_t var_4 = __riscv_vssub_vx_i16m8_mu(var_6, var_12, var_49,
> var_10, 43);
> // -27921, -25052, -17, -20337, 15054, 1382, -12, -16, 16159, -32768,
> 17832, -12646, 16746, 20, -15, -16, 4, 7798, 14967, 3, -29916, 11, -6168,
> -32768, 14361, -14023, -32768, -12646, 10, -12646, 18748, -12646, 8473,
> -32768, -32768, 16, -32768, -14720, -11479, 6985, -24591, -28243, 11
> __riscv_vsetvl_e16m8(16);
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c
> index c7267fcbfce..667a7656ce1 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA,
> 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA,
> 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c
> index 3694a95ed24..eefdf455bca 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
> index b65f9935692..4b24b971cba 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
> @@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n)
> for (int i = 0; i < n; i++) {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_i64m1 (out + i + 2, v4, 4);
> }
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c
> index fb401bd1978..7ffedd5ceb9 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -66,8 +66,8 @@ void f3 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAA, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -83,8 +83,8 @@ void f4 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -100,8 +100,8 @@ void f5 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -117,7 +117,7 @@ void f6 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, x, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, x, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c
> index 408359f29c4..612213a6036 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -66,7 +66,7 @@ void f3 (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAA, 0,4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAA, 0,4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c
> index c6d3981fd83..86825c088b1 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 0, 4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 0, 4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c
> index 963a1579504..94bff68ba5e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0, 4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2,
> 0xAAAAAAAAAAAAAAAA, 0, 4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2,
> 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
> index b04e03b5894..a3d08de06c4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 0, 4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 0, 4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
> index 3df45b64480..99acc51b4ff 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
> @@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n)
> for (int i = 0; i < n; i++) {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + i + 2, 4);
> - vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 0, 4);
> - vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 0, 4);
> + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4);
> + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_u64m1 (out + i + 2, v4, 4);
> }
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c
> index 11b6b1862af..9127b869f53 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -66,8 +66,8 @@ void f3 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAA, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -83,8 +83,8 @@ void f4 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -100,8 +100,8 @@ void f5 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -117,7 +117,7 @@ void f6 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, x, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, x, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c
> index 11b6f724359..d70789e1810 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -66,7 +66,7 @@ void f3 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAA, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAA, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c
> index bd1fd27ad93..e02b21554a8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c
> index 6696d4c1867..8cd9c4d09ba 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA,
> 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA,
> 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c
> index 80bba2ae796..6090a1da69d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
> index ecbb3e3d386..d595c446503 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
> @@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n)
> for (int i = 0; i < n; i++) {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4);
> - vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 0, 4);
> - vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 0, 4);
> + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4);
> + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_i64m1 (out + i + 2, v4, 4);
> }
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c
> index d7ec2688e64..9722f5e6118 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, -16, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, -16, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, -16, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, -16, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 15, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 15, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 15, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 15, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 16, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 16, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 16, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 16, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> @@ -66,7 +66,7 @@ void f3 (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAA, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 0xAAAAAAA, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 0xAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c
> index ae6a40540e6..066365dc744 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAA, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c
> index 60461f86a28..bfc6773f198 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2,
> 0xAAAAAAAAAAAAAAAA, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2,
> 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c
> index 088d797dc9f..05a7a1d9e65 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c
> @@ -6,8 +6,8 @@ void f (void * in, void *out, uint64_t x, int n)
> {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_u64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
> index 7d00b8499ef..0b51175f66c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
> @@ -7,8 +7,8 @@ void f (void * in, void *out, uint64_t x, int n)
> for (int i = 0; i < n; i++) {
> vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + 1, 4);
> vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + i + 2, 4);
> - vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 0, 4);
> - vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 0, 4);
> + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 4);
> + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 4);
> __riscv_vse64_v_u64m1 (out + i + 2, v4, 4);
> }
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c
> index c13ed674c67..d1283d89a93 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -66,8 +66,8 @@ void f3 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAA, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAA, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -83,8 +83,8 @@ void f4 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -100,8 +100,8 @@ void f5 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -117,7 +117,7 @@ void f6 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, x, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, x, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c
> index 328d1d62a70..ed7477b3ca8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c
> @@ -15,8 +15,8 @@ void f0 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -32,8 +32,8 @@ void f1 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -49,8 +49,8 @@ void f2 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> @@ -66,7 +66,7 @@ void f3 (void * in, void *out, int64_t x, int n)
> {
> vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
> vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
> - vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAA, 0,4);
> - vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAA, 0,4);
> + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAA, 4);
> + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAA, 4);
> __riscv_vse64_v_i64m1 (out + 2, v4, 4);
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
> new file mode 100644
> index 00000000000..2b824458cf5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
> @@ -0,0 +1,24 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test_vsadd_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vsadd_vv_i8mf8 (op1, op2, __RISCV_VXRM_RNU, vl); /* {
> dg-error {too many arguments to function '__riscv_vsadd_vv_i8mf8'} } */
> +}
> +
> +vuint8mf8_t test_vsaddu_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t op2,
> size_t vl)
> +{
> + return __riscv_vsaddu_vv_u8mf8 (op1, op2, __RISCV_VXRM_RNU, vl); /* {
> dg-error {too many arguments to function '__riscv_vsaddu_vv_u8mf8'} } */
> +}
> +
> +vint8mf8_t test_vssub_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vssub_vv_i8mf8 (op1, op2, __RISCV_VXRM_RNU, vl); /* {
> dg-error {too many arguments to function '__riscv_vssub_vv_i8mf8'} } */
> +}
> +
> +vuint8mf8_t test_vssubu_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t op2,
> size_t vl)
> +{
> + return __riscv_vssubu_vv_u8mf8 (op1, op2, __RISCV_VXRM_RNU, vl); /* {
> dg-error {too many arguments to function '__riscv_vssubu_vv_u8mf8'} } */
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
> new file mode 100644
> index 00000000000..41e34cd3844
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
> @@ -0,0 +1,81 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test_vaadd_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vaadd_vv_i8mf8 (op1, op2, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vuint8mf8_t test_vaaddu_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t op2,
> size_t vl)
> +{
> + return __riscv_vaaddu_vv_u8mf8 (op1, op2, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vint8mf8_t test_vasub_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vasub_vv_i8mf8 (op1, op2, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vuint8mf8_t test_vasubu_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t op2,
> size_t vl)
> +{
> + return __riscv_vasubu_vv_u8mf8 (op1, op2, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vint8mf8_t test_vnclip_wv_i8mf8 (vint16mf4_t op1, vuint8mf8_t shift,
> size_t vl)
> +{
> + return __riscv_vnclip_wv_i8mf8 (op1, shift, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vuint8mf8_t test_vnclipu_wv_u8mf8 (vuint16mf4_t op1, vuint8mf8_t shift,
> size_t vl)
> +{
> + return __riscv_vnclipu_wv_u8mf8 (op1, shift, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vint8mf8_t test_vsmul_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vsmul_vv_i8mf8 (op1, op2, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vint8mf8_t test_vssra_vv_i8mf8 (vint8mf8_t op1, vuint8mf8_t shift, size_t
> vl)
> +{
> + return __riscv_vssra_vv_i8mf8 (op1, shift, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vuint8mf8_t test_vssrl_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t shift,
> size_t vl)
> +{
> + return __riscv_vssrl_vv_u8mf8 (op1, shift, __RISCV_VXRM_RNU, vl);
> +}
> +
> +vint8mf8_t test_vsadd_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vsadd_vv_i8mf8 (op1, op2, vl);
> +}
> +vuint8mf8_t test_vsaddu_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t op2,
> size_t vl)
> +{
> + return __riscv_vsaddu_vv_u8mf8 (op1, op2, vl);
> +}
> +vint8mf8_t test_vssub_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl)
> +{
> + return __riscv_vssub_vv_i8mf8 (op1, op2, vl);
> +}
> +vuint8mf8_t test_vssubu_vv_u8mf8 (vuint8mf8_t op1, vuint8mf8_t op2,
> size_t vl)
> +{
> + return __riscv_vssubu_vv_u8mf8 (op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vaaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vssrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
> +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*0} 9 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
> index 1b418b82f36..297e651db63 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
> @@ -165,7 +165,7 @@ void f16 (int8_t* base1,int8_t* base2,int8_t* out,int
> n)
> {
> vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
> for (int i = 0; i < n; i++){
> - v = __riscv_vsadd_vv_i8mf4 (v, v, 0, 32);
> + v = __riscv_vsadd_vv_i8mf4 (v, v, 32);
> v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
> }
> __riscv_vse8_v_i8mf4 (out, v, 32);
> @@ -175,7 +175,7 @@ void f17 (int8_t* base1,int8_t* base2,int8_t* out,int
> n)
> {
> vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
> for (int i = 0; i < n; i++){
> - v = __riscv_vsadd_vx_i8mf4 (v, 100, 0, 32);
> + v = __riscv_vsadd_vx_i8mf4 (v, 100, 32);
> v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
> }
> __riscv_vse8_v_i8mf4 (out, v, 32);
> --
> 2.17.1
>
>
>
next prev parent reply other threads:[~2023-07-28 6:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-28 5:52 Li Xu
2023-07-28 6:42 ` juzhe.zhong
2023-07-28 6:45 ` Kito Cheng [this message]
2023-07-28 7:21 ` Li, Pan2
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