[RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Kito Cheng]

Bit manipulation extension[1] is finishing the public review and waiting for
the rest of the ratification process, I believe that will become a ratified
extension soon, so I think it's time to submit to upstream for review now :)

As the title included RFC, it's not a rush to merge to trunk yet, I would
like to merge that until it is officially ratified.

This patch set is the implementation of bit-manipulation extension, which
includes zba, zbb, zbc and zbs extension, but only included in instruction/md
pattern only, no intrinsic function implementation.

Most work is done by Jim Willson and many other contributors
on https://github.com/riscv-collab/riscv-gcc.


[1] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0

[RFC PATCH 1/8] RISC-V: Minimal support of bitmanip extension

[Kito Cheng]

2021-09-23  Kito Cheng  <kito.cheng@sifive.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.c (riscv_ext_version_table):
	Add zba, zbb, zbc and zbs.
	(riscv_ext_flag_table): Ditto.
	* config/riscv/riscv-opts.h (MASK_ZBA): New.
	(MASK_ZBB): Ditto.
	(MASK_ZBC): Ditto.
	(MASK_ZBS): Ditto.
	(TARGET_ZBA): Ditto.
	(TARGET_ZBB): Ditto.
	(TARGET_ZBC): Ditto.
	(TARGET_ZBS): Ditto.
	* config/riscv/riscv.opt (riscv_zb_subext): New.
---
 gcc/common/config/riscv/riscv-common.c | 10 ++++++++++
 gcc/config/riscv/riscv-opts.h          | 10 ++++++++++
 gcc/config/riscv/riscv.opt             |  3 +++
 3 files changed, 23 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 10868fd417d..37b6ea80086 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -101,6 +101,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -906,6 +911,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
 
+  {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
+  {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
+  {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
+  {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f4cf6ca4b82..2efc4b80f1f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,4 +73,14 @@ enum stack_protector_guard {
 #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
 
+#define MASK_ZBA      (1 << 0)
+#define MASK_ZBB      (1 << 1)
+#define MASK_ZBC      (1 << 2)
+#define MASK_ZBS      (1 << 3)
+
+#define TARGET_ZBA    ((riscv_zb_subext & MASK_ZBA) != 0)
+#define TARGET_ZBB    ((riscv_zb_subext & MASK_ZBB) != 0)
+#define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
+#define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 5ff85c21430..15bf89e17c2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
 TargetVariable
 int riscv_zi_subext
 
+TargetVariable
+int riscv_zb_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.33.0

[RFC PATCH 2/8] RISC-V: Implement instruction patterns for ZBA extension.

[Kito Cheng]

From: Jim Wilson <jimw@sifive.com>

2021-09-23 Jim Wilson <jimw@sifive.com>
	   Kito Cheng <kito.cheng@sifive.com>
	   Jia-Wei Chen <jiawei@iscas.ac.cn>

gcc/ChangeLog:

	* config/riscv/bitmanip.md (*zero_extendsidi2_bitmanip): New.
	(*shNadd): Ditto.
	(*shNadduw): Ditto.
	(*add.uw): Ditto.
	(*slliuw): Ditto.
	* config/riscv/riscv.c (riscv_extend_cost): Handle cost model
	for zba extension.
	(riscv_rtx_costs): Ditto.
	* config/riscv/riscv.md: Include bitmanip.md
	(type): Add bitmanip bype.
	(zero_extendsidi2): Change to define_expand pattern.
	(*zero_extendsidi2_internal): New.
	(zero_extendsidi2_shifted): Disable for ZBA.

2021-09-23 Kito Cheng <kito.cheng@sifive.com>
	   Jia-Wei Chen <jiawei@iscas.ac.cn>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zba-adduw.c: New.
	* gcc.target/riscv/zba-shNadd-01.c: Ditto.
	* gcc.target/riscv/zba-shNadd-02.c: Ditto.
	* gcc.target/riscv/zba-shNadd-03.c: Ditto.
	* gcc.target/riscv/zba-slliuw.c: Ditto.
	* gcc.target/riscv/zba-zextw.c: Ditto.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>
---
 gcc/config/riscv/bitmanip.md                  | 76 +++++++++++++++++++
 gcc/config/riscv/riscv.md                     | 14 +++-
 gcc/testsuite/gcc.target/riscv/zba-adduw.c    | 12 +++
 .../gcc.target/riscv/zba-shNadd-01.c          | 19 +++++
 .../gcc.target/riscv/zba-shNadd-02.c          | 19 +++++
 .../gcc.target/riscv/zba-shNadd-03.c          | 31 ++++++++
 gcc/testsuite/gcc.target/riscv/zba-slliuw.c   | 11 +++
 gcc/testsuite/gcc.target/riscv/zba-zextw.c    | 10 +++
 8 files changed, 188 insertions(+), 4 deletions(-)
 create mode 100644 gcc/config/riscv/bitmanip.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
new file mode 100644
index 00000000000..3849d21dc15
--- /dev/null
+++ b/gcc/config/riscv/bitmanip.md
@@ -0,0 +1,76 @@
+;; Machine description for RISC-V Bit Manipulation operations.
+;; Copyright (C) 2021 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; ZBA extension.
+
+(define_insn "*zero_extendsidi2_bitmanip"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_64BIT && TARGET_ZBA"
+  "@
+   zext.w\t%0,%1
+   lwu\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "DI")])
+
+(define_insn "*shNadd"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
+			  (match_operand:QI 2 "immediate_operand" "I"))
+		(match_operand:X 3 "register_operand" "r")))]
+  "TARGET_ZBA
+   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
+  "sh%2add\t%0,%1,%3"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "<X:MODE>")])
+
+(define_insn "*shNadduw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI
+	  (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+			     (match_operand:QI 2 "immediate_operand" "I"))
+		 (match_operand 3 "immediate_operand" ""))
+	  (match_operand:DI 4 "register_operand" "r")))]
+  "TARGET_64BIT && TARGET_ZBA
+   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
+   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
+  "sh%2add.uw\t%0,%1,%4"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "DI")])
+
+(define_insn "*add.uw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (zero_extend:DI
+		   (match_operand:SI 1 "register_operand" "r"))
+		 (match_operand:DI 2 "register_operand" "r")))]
+  "TARGET_64BIT && TARGET_ZBA"
+  "add.uw\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "DI")])
+
+(define_insn "*slliuw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+			   (match_operand:QI 2 "immediate_operand" "I"))
+		(match_operand 3 "immediate_operand" "")))]
+  "TARGET_64BIT && TARGET_ZBA
+   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
+  "slli.uw\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "DI")])
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f88877fd596..dedfd20e5b3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -170,7 +170,7 @@
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
-   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
+   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,
@@ -1302,11 +1302,16 @@
 
 ;; Extension insns.
 
-(define_insn_and_split "zero_extendsidi2"
+(define_expand "zero_extendsidi2"
+  [(set (match_operand:DI 0 "register_operand")
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
+  "TARGET_64BIT")
+
+(define_insn_and_split "*zero_extendsidi2_internal"
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
   "@
    #
    lwu\t%0,%1"
@@ -2078,7 +2083,7 @@
 			   (match_operand:QI 2 "immediate_operand" "I"))
 		(match_operand 3 "immediate_operand" "")))
    (clobber (match_scratch:DI 4 "=&r"))]
-  "TARGET_64BIT
+  "TARGET_64BIT && !TARGET_ZBA
    && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)"
   "#"
   "&& reload_completed"
@@ -2845,6 +2850,7 @@
   "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
   [(set_attr "length" "12")])
 
+(include "bitmanip.md")
 (include "sync.md")
 (include "peephole.md")
 (include "pic.md")
diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
new file mode 100644
index 00000000000..cac1e849728
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
+
+int foo(int n, unsigned char *arr, unsigned y){
+  int s = 0;
+  unsigned x = 0;
+  for (;x<n;x++)
+    s += arr[x+y];
+  return s;
+}
+
+/* { dg-final { scan-assembler "add.uw" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
new file mode 100644
index 00000000000..aaabaf5e4e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
+
+long test_1(long a, long b)
+{
+  return a + (b << 1);
+}
+long test_2(long a, long b)
+{
+  return a + (b << 2);
+}
+long test_3(long a, long b)
+{
+  return a + (b << 3);
+}
+
+/* { dg-final { scan-assembler-times "sh1add" 1 } } */
+/* { dg-final { scan-assembler-times "sh2add" 1 } } */
+/* { dg-final { scan-assembler-times "sh3add" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
new file mode 100644
index 00000000000..8dfea4a1a85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
+
+long test_1(long a, long b)
+{
+  return a + (b << 1);
+}
+long test_2(long a, long b)
+{
+  return a + (b << 2);
+}
+long test_3(long a, long b)
+{
+  return a + (b << 3);
+}
+
+/* { dg-final { scan-assembler-times "sh1add" 1 } } */
+/* { dg-final { scan-assembler-times "sh2add" 1 } } */
+/* { dg-final { scan-assembler-times "sh3add" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
new file mode 100644
index 00000000000..b2ea231a255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
+
+/* RV64 only.  */
+int foos(short *x, int n){
+  return x[n];
+}
+int fooi(int *x, int n){
+  return x[n];
+}
+int fooll(long long *x, int n){
+  return x[n];
+}
+
+/* RV64 only.  */
+int ufoos(short *x, unsigned int n){
+  return x[n];
+}
+int ufooi(int *x, unsigned int n){
+  return x[n];
+}
+int ufooll(long long *x, unsigned int n){
+  return x[n];
+}
+
+/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */
+/* { dg-final { scan-assembler-times "sh2add\t" 1 } } */
+/* { dg-final { scan-assembler-times "sh3add\t" 1 } } */
+/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
+/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
+/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
new file mode 100644
index 00000000000..50399f68e08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
+
+long
+foo (long i)
+{
+  return (long)(unsigned int)i << 10;
+}
+/* XXX: This pattern need combine improvement or intermediate instruction
+ *      from zbs.   */
+/* { dg-final { scan-assembler-not "slli.uw" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
new file mode 100644
index 00000000000..26fd64d70ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
+
+long
+foo (long i)
+{
+  return (long)(unsigned int)i;
+}
+/* XXX: This pattern require combine improvement.   */
+/* { dg-final { scan-assembler-not "slli.uw" } } */
-- 
2.33.0

[RFC PATCH 3/8] RISC-V: Cost model for zba extension.

[Kito Cheng]

2021-09-23 Kito Cheng <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_extend_cost): Handle cost model
	for zba extension.
	(riscv_rtx_costs): Ditto.
---
 gcc/config/riscv/riscv.c | 81 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 576960bb37c..cc58b7041ac 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1702,6 +1702,10 @@ riscv_extend_cost (rtx op, bool unsigned_p)
     /* We can use ANDI.  */
     return COSTS_N_INSNS (1);
 
+  /* ZBA provide zext.w.  */
+  if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
+    return COSTS_N_INSNS (1);
+
   if (!unsigned_p && GET_MODE (op) == SImode)
     /* We can use SEXT.W.  */
     return COSTS_N_INSNS (1);
@@ -1775,6 +1779,21 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
       return false;
 
     case AND:
+      /* slli.uw pattern for zba.  */
+      if (TARGET_ZBA && TARGET_64BIT && mode == DImode
+	  && GET_CODE (XEXP (x, 0)) == ASHIFT)
+	{
+	  rtx and_rhs = XEXP (x, 1);
+	  rtx ashift_lhs = XEXP (XEXP (x, 0), 0);
+	  rtx ashift_rhs = XEXP (XEXP (x, 0), 1);
+	  if (REG_P (ashift_lhs)
+	      && CONST_INT_P (ashift_rhs)
+	      && CONST_INT_P (and_rhs)
+	      && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
+	    *total = COSTS_N_INSNS (1);
+	    return true;
+	}
+      gcc_fallthrough ();
     case IOR:
     case XOR:
       /* Double-word operations use two single-word operations.  */
@@ -1866,6 +1885,68 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 
     case MINUS:
     case PLUS:
+      /* add.uw pattern for zba.  */
+      if (TARGET_ZBA
+	  && (TARGET_64BIT && (mode == DImode))
+	  && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+	  && REG_P (XEXP (XEXP (x, 0), 0))
+	  && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      /* shNadd pattern for zba.  */
+      if (TARGET_ZBA
+	  && ((!TARGET_64BIT && (mode == SImode)) ||
+	      (TARGET_64BIT && (mode == DImode)))
+	  && (GET_CODE (XEXP (x, 0)) == ASHIFT)
+	  && REG_P (XEXP (XEXP (x, 0), 0))
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 0))
+	  && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 0)), 1, 3))
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      /* shNadd.uw pattern for zba.
+	 [(set (match_operand:DI 0 "register_operand" "=r")
+	       (plus:DI
+		 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+				    (match_operand:QI 2 "immediate_operand" "I"))
+			 (match_operand 3 "immediate_operand" ""))
+		 (match_operand:DI 4 "register_operand" "r")))]
+	 "TARGET_64BIT && TARGET_ZBA
+	  && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
+	  && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
+      */
+      if (TARGET_ZBA
+	  && (TARGET_64BIT && (mode == DImode))
+	  && (GET_CODE (XEXP (x, 0)) == AND)
+	  && (REG_P (XEXP (x, 1))))
+	{
+	  do {
+	    rtx and_lhs = XEXP (XEXP (x, 0), 0);
+	    rtx and_rhs = XEXP (XEXP (x, 0), 1);
+	    if (GET_CODE (and_lhs) != ASHIFT)
+	      break;
+	    if (!CONST_INT_P (and_rhs))
+	      break;
+
+	    rtx ashift_lhs = XEXP (and_lhs, 0);
+	    rtx ashift_rhs = XEXP (and_lhs, 1);
+
+	    if (!CONST_INT_P (ashift_rhs)
+		|| !IN_RANGE (INTVAL (ashift_rhs), 1, 3))
+	      break;
+
+	    if (CONST_INT_P (and_rhs)
+		&& ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
+	      {
+		*total = COSTS_N_INSNS (1);
+		return true;
+	      }
+	  } while (false);
+	}
+
       if (float_mode_p)
 	*total = tune_param->fp_add[mode == DFmode];
       else
-- 
2.33.0

[RFC PATCH 4/8] RISC-V: Implement instruction patterns for ZBB extension.

[Kito Cheng]

From: Jim Wilson <jimw@sifive.com>

2021-09-23 Jim Wilson <jimw@sifive.com>
	   Kito Cheng <kito.cheng@sifive.com>
	   Jia-Wei Chen <jiawei@iscas.ac.cn>

gcc/ChangeLog:

	* config/riscv/bitmanip.md (bitmanip_bitwise): New.
	(bitmanip_minmax): New.
	(clz_ctz_pcnt): New.
	(bitmanip_optab): New.
	(bitmanip_insn): New.
	(*<optab>_not<mode>): New.
	(*xor_not<mode>): New.
	(<bitmanip_optab>si2): New.
	(*<bitmanip_optab>disi2): New.
	(<bitmanip_optab>di2): New.
	(*zero_extendhi<GPR:mode>2_bitmanip): New.
	(*extend<SHORT:mode><SUPERQI:mode>2_zbb): New.
	(*zero_extendhi<GPR:mode>2_zbb): New.
	(rotrsi3): New.
	(rotrdi3): New.
	(rotrsi3_sext): New.
	(rotlsi3): New.
	(rotldi3): New.
	(rotlsi3_sext): New.
	(bswap<mode>2): New.
	(<bitmanip_optab><mode>3): New.
	* config/riscv/riscv.c (riscv_extend_cost): Handle cost model
	for zbb extension.
	(riscv_rtx_costs): Ditto.
	* config/riscv/riscv.md (type): Add rotate.
	(zero_extendhi<GPR:mode>2): Change to define_expand pattern.
	(*zero_extendhi<GPR:mode>2): New.
	(extend<SHORT:mode><SUPERQI:mode>2): Change to define_expand pattern.
	(*extend<SHORT:mode><SUPERQI:mode>2): New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-andn-orn-xnor-01.c: New.
	* gcc.target/riscv/zbb-andn-orn-xnor-02.c: Ditto.
	* gcc.target/riscv/zbb-min-max.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-01.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-02.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-03.c: Ditto.
	* gcc.target/riscv/zbbw.c: Ditto.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>
---
 gcc/config/riscv/bitmanip.md                  | 164 ++++++++++++++++++
 gcc/config/riscv/riscv.md                     |  21 ++-
 .../gcc.target/riscv/zbb-andn-orn-xnor-01.c   |  21 +++
 .../gcc.target/riscv/zbb-andn-orn-xnor-02.c   |  21 +++
 gcc/testsuite/gcc.target/riscv/zbb-min-max.c  |  31 ++++
 .../gcc.target/riscv/zbb-rol-ror-01.c         |  16 ++
 .../gcc.target/riscv/zbb-rol-ror-02.c         |  16 ++
 .../gcc.target/riscv/zbb-rol-ror-03.c         |  17 ++
 gcc/testsuite/gcc.target/riscv/zbbw.c         |  25 +++
 9 files changed, 327 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 3849d21dc15..4d624514049 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -17,6 +17,30 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
+(define_code_iterator bitmanip_bitwise [and ior])
+
+(define_code_iterator bitmanip_minmax [smin umin smax umax])
+
+(define_code_iterator clz_ctz_pcnt [clz ctz popcount])
+
+(define_code_attr bitmanip_optab [(smin "smin")
+				  (smax "smax")
+				  (umin "umin")
+				  (umax "umax")
+				  (clz "clz")
+				  (ctz "ctz")
+				  (popcount "popcount")])
+
+
+(define_code_attr bitmanip_insn [(smin "min")
+				 (smax "max")
+				 (umin "minu")
+				 (umax "maxu")
+				 (clz "clz")
+				 (ctz "ctz")
+				 (popcount "cpop")])
+
+
 ;; ZBA extension.
 
 (define_insn "*zero_extendsidi2_bitmanip"
@@ -74,3 +98,143 @@
   "slli.uw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "DI")])
+
+;; ZBB extension.
+
+(define_insn "*<optab>_not<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
+                            (match_operand:X 2 "register_operand" "r")))]
+  "TARGET_ZBB"
+  "<insn>n\t%0,%2,%1"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "<X:MODE>")])
+
+(define_insn "*xor_not<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (not:X (xor:X (match_operand:X 1 "register_operand" "r")
+                      (match_operand:X 2 "register_operand" "r"))))]
+  "TARGET_ZBB"
+  "xnor\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "<X:MODE>")])
+
+(define_insn "<bitmanip_optab>si2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
+  "TARGET_ZBB"
+  { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "SI")])
+
+(define_insn "*<bitmanip_optab>disi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (sign_extend:DI
+          (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "<bitmanip_insn>w\t%0,%1"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "SI")])
+
+(define_insn "<bitmanip_optab>di2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "<bitmanip_insn>\t%0,%1"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "DI")])
+
+(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
+  [(set (match_operand:GPR 0 "register_operand" "=r,r")
+        (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_ZBB"
+  "@
+   zext.h\t%0,%1
+   lhu\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
+  [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
+	(sign_extend:SUPERQI
+	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
+  "TARGET_ZBB"
+  "@
+   sext.<SHORT:size>\t%0,%1
+   l<SHORT:size>\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "<SUPERQI:MODE>")])
+
+(define_insn "*zero_extendhi<GPR:mode>2_zbb"
+  [(set (match_operand:GPR    0 "register_operand"     "=r,r")
+	(zero_extend:GPR
+	    (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
+  "TARGET_ZBB"
+  "@
+   zext.h\t%0,%1
+   lhu\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "HI")])
+
+(define_insn "rotrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
+		     (match_operand:QI 2 "arith_operand" "rI")))]
+  "TARGET_ZBB"
+  { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "rotrdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
+		     (match_operand:QI 2 "arith_operand" "rI")))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "ror%i2\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "rotrsi3_sext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
+				     (match_operand:QI 2 "register_operand" "r"))))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "rorw\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "rotlsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:QI 2 "register_operand" "r")))]
+  "TARGET_ZBB"
+  { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "rotldi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(rotate:DI (match_operand:DI 1 "register_operand" "r")
+		   (match_operand:QI 2 "register_operand" "r")))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "rol\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "rotlsi3_sext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
+				   (match_operand:QI 2 "register_operand" "r"))))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "rolw\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "bswap<mode>2"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (bswap:X (match_operand:X 1 "register_operand" "r")))]
+  "TARGET_64BIT && TARGET_ZBB"
+  "rev8\t%0,%1"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "<bitmanip_optab><mode>3"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
+			   (match_operand:X 2 "register_operand" "r")))]
+  "TARGET_ZBB"
+  "<bitmanip_insn>\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dedfd20e5b3..25186067646 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -170,7 +170,7 @@
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
-   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
+   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,
@@ -1326,11 +1326,17 @@
   [(set_attr "move_type" "shift_shift,load")
    (set_attr "mode" "DI")])
 
-(define_insn_and_split "zero_extendhi<GPR:mode>2"
+(define_expand "zero_extendhi<GPR:mode>2"
+  [(set (match_operand:GPR    0 "register_operand")
+	(zero_extend:GPR
+	    (match_operand:HI 1 "nonimmediate_operand")))]
+  "")
+
+(define_insn_and_split "*zero_extendhi<GPR:mode>2"
   [(set (match_operand:GPR    0 "register_operand"     "=r,r")
 	(zero_extend:GPR
 	    (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
-  ""
+  "!TARGET_ZBB"
   "@
    #
    lhu\t%0,%1"
@@ -1377,11 +1383,16 @@
   [(set_attr "move_type" "move,load")
    (set_attr "mode" "DI")])
 
-(define_insn_and_split "extend<SHORT:mode><SUPERQI:mode>2"
+(define_expand "extend<SHORT:mode><SUPERQI:mode>2"
+  [(set (match_operand:SUPERQI 0 "register_operand")
+	(sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand")))]
+  "")
+
+(define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
   [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
 	(sign_extend:SUPERQI
 	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
-  ""
+  "!TARGET_ZBB"
   "@
    #
    l<SHORT:size>\t%0,%1"
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
new file mode 100644
index 00000000000..0037dea5647
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+
+unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
+{
+return rs1 & ~rs2;
+}
+
+unsigned long long foo2(unsigned long long rs1, unsigned long long rs2)
+{
+return rs1 | ~rs2;
+}
+
+unsigned long long foo3(unsigned long long rs1, unsigned long long rs2)
+{
+return rs1 ^ ~rs2;
+}
+
+/* { dg-final { scan-assembler-times "andn" 2 } } */
+/* { dg-final { scan-assembler-times "orn" 2 } } */
+/* { dg-final { scan-assembler-times "xnor" 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
new file mode 100644
index 00000000000..b0c1e40c554
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+
+unsigned int foo1(unsigned int rs1, unsigned int rs2)
+{
+return rs1 & ~rs2;
+}
+
+unsigned int foo2(unsigned  int rs1, unsigned  int rs2)
+{
+return rs1 | ~rs2;
+}
+
+unsigned int foo3(unsigned int rs1, unsigned int rs2)
+{
+return rs1 ^ ~rs2;
+}
+
+/* { dg-final { scan-assembler-times "andn" 2 } } */
+/* { dg-final { scan-assembler-times "orn" 2 } } */
+/* { dg-final { scan-assembler-times "xnor" 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
new file mode 100644
index 00000000000..f44c398ea08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+
+long
+foo1 (long i, long j)
+{
+  return i < j ? i : j;
+}
+
+long
+foo2 (long i, long j)
+{
+  return i > j ? i : j;
+}
+
+unsigned long
+foo3 (unsigned long i, unsigned long j)
+{
+  return i < j ? i : j;
+}
+
+unsigned long
+foo4 (unsigned long i, unsigned long j)
+{
+  return i > j ? i : j;
+}
+
+/* { dg-final { scan-assembler-times "min" 3 } } */
+/* { dg-final { scan-assembler-times "max" 3 } } */
+/* { dg-final { scan-assembler-times "minu" 1 } } */
+/* { dg-final { scan-assembler-times "maxu" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
new file mode 100644
index 00000000000..958966289df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+
+unsigned long foo1(unsigned long rs1, unsigned long rs2)
+{
+    long shamt = rs2 & (64 - 1);
+    return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1)));
+}
+unsigned long foo2(unsigned long rs1, unsigned long rs2)
+{
+    unsigned long shamt = rs2 & (64 - 1);
+    return (rs1 >> shamt) | (rs1 << ((64 - shamt) & (64 - 1)));
+}
+
+/* { dg-final { scan-assembler-times "rol" 2 } } */
+/* { dg-final { scan-assembler-times "ror" 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
new file mode 100644
index 00000000000..24b482f2145
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+
+unsigned int foo1(unsigned int rs1, unsigned int rs2)
+{
+    unsigned int shamt = rs2 & (32 - 1);
+    return (rs1 << shamt) | (rs1 >> ((32 - shamt) & (32 - 1)));
+}
+unsigned int foo2(unsigned int rs1, unsigned int rs2)
+{
+    unsigned int shamt = rs2 & (32 - 1);
+    return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
+}
+
+/* { dg-final { scan-assembler-times "rol" 2 } } */
+/* { dg-final { scan-assembler-times "ror" 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
new file mode 100644
index 00000000000..ffde7c9cd58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+
+/* RV64 only*/
+unsigned int rol(unsigned int rs1, unsigned int rs2)
+{
+    int shamt = rs2 & (32 - 1);
+    return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (32 - 1)));
+}
+unsigned int ror(unsigned int rs1, unsigned int rs2)
+{
+    int shamt = rs2 & (64 - 1);
+    return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
+}
+
+/* { dg-final { scan-assembler-times "rolw" 1 } } */
+/* { dg-final { scan-assembler-times "rorw" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
new file mode 100644
index 00000000000..236ddf7b583
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbbw.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+
+int
+clz (int i)
+{
+  return __builtin_clz (i);
+}
+
+int
+ctz (int i)
+{
+  return __builtin_ctz (i);
+}
+
+int
+popcount (int i)
+{
+  return __builtin_popcount (i);
+}
+
+
+/* { dg-final { scan-assembler-times "clzw" 1 } } */
+/* { dg-final { scan-assembler-times "ctzw" 1 } } */
+/* { dg-final { scan-assembler-times "cpopw" 1 } } */
-- 
2.33.0

[RFC PATCH 5/8] RISC-V: Cost model for zbb extension.

[Kito Cheng]

2021-09-23 Kito Cheng <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_extend_cost): Handle cost model
	for zbb extension.
	(riscv_rtx_costs): Ditto.
---
 gcc/config/riscv/riscv.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index cc58b7041ac..10f7bd21f8d 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1706,6 +1706,16 @@ riscv_extend_cost (rtx op, bool unsigned_p)
   if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
     return COSTS_N_INSNS (1);
 
+  /* ZBB provide zext.h, sext.b and sext.h.  */
+  if (TARGET_ZBB)
+    {
+      if (!unsigned_p && GET_MODE (op) == QImode)
+	return COSTS_N_INSNS (1);
+
+      if (GET_MODE (op) == HImode)
+	return COSTS_N_INSNS (1);
+    }
+
   if (!unsigned_p && GET_MODE (op) == SImode)
     /* We can use SEXT.W.  */
     return COSTS_N_INSNS (1);
@@ -1796,6 +1806,13 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
       gcc_fallthrough ();
     case IOR:
     case XOR:
+      /* orn, andn and xorn pattern for zbb.  */
+      if (TARGET_ZBB
+	  && GET_CODE (XEXP (x, 0)) == NOT)
+	{
+	  *total = riscv_binary_cost (x, 1, 2);
+	  return true;
+	}
       /* Double-word operations use two single-word operations.  */
       *total = riscv_binary_cost (x, 1, 2);
       return false;
-- 
2.33.0

[RFC PATCH 6/8] RISC-V: Use li and rori to load constants.

[Kito Cheng]

From: Jim Wilson <jimw@sifive.com>

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_build_integer_1): Build integer
	with rotate.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-li-rotr.c: New.
---
 gcc/config/riscv/riscv.c                     | 41 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 35 +++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 10f7bd21f8d..66daebbbc8f 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -461,6 +461,47 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
 	}
     }
 
+  if (cost > 2 && TARGET_64BIT && TARGET_ZBB)
+    {
+      int leading_ones = clz_hwi (~value);
+      int trailing_ones = ctz_hwi (~value);
+
+      /* If all bits are one except a few that are zero, and the zero bits
+	 are within a range of 11 bits, and at least one of the upper 32-bits
+	 is a zero, then we can generate a constant by loading a small
+	 negative constant and rotating.  */
+      if (leading_ones < 32
+	  && ((64 - leading_ones - trailing_ones) < 12))
+	{
+	  codes[0].code = UNKNOWN;
+	  /* The sign-bit might be zero, so just rotate to be safe.  */
+	  codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones)
+			    | (value << (64 - trailing_ones)));
+	  codes[1].code = ROTATERT;
+	  codes[1].value = 64 - trailing_ones;
+	  cost = 2;
+	}
+      /* Handle the case where the 11 bit range of zero bits wraps around.  */
+      else
+	{
+	  int upper_trailing_ones = ctz_hwi (~value >> 32);
+	  int lower_leading_ones = clz_hwi (~value << 32);
+
+	  if (upper_trailing_ones < 32 && lower_leading_ones < 32
+	      && ((64 - upper_trailing_ones - lower_leading_ones) < 12))
+	    {
+	      codes[0].code = UNKNOWN;
+	      /* The sign-bit might be zero, so just rotate to be safe.  */
+	      codes[0].value = ((value << (32 - upper_trailing_ones))
+				| ((unsigned HOST_WIDE_INT) value
+				   >> (32 + upper_trailing_ones)));
+	      codes[1].code = ROTATERT;
+	      codes[1].value = 32 - upper_trailing_ones;
+	      cost = 2;
+	    }
+	}
+    }
+
   gcc_assert (cost <= RISCV_MAX_INTEGER_OPS);
   return cost;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
new file mode 100644
index 00000000000..03254ed9150
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+
+long
+li_rori (void)
+{
+  return 0xffff77ffffffffffL;
+}
+
+long
+li_rori_2 (void)
+{
+  return 0x77ffffffffffffffL;
+}
+
+long
+li_rori_3 (void)
+{
+  return 0xfffffffeefffffffL;
+}
+
+long
+li_rori_4 (void)
+{
+  return 0x5ffffffffffffff5L;
+}
+
+long
+li_rori_5 (void)
+{
+  return 0xaffffffffffffffaL;
+}
+
+
+/* { dg-final { scan-assembler-times "rori\t" 5 } } */
-- 
2.33.0

[RFC PATCH 7/8] RISC-V: Implement instruction patterns for ZBS extension.

[Kito Cheng]

From: Jim Wilson <jimw@sifive.com>

2021-09-23 Jim Wilson <jimw@sifive.com>
	   Kito Cheng <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/bitmanip.md (shiftm1): New.
	(*bset<mode>): Ditto.
	(*bset<mode>_mask): Ditto.
	(*bset<mode>_1): Ditto.
	(*bset<mode>_1_mask): Ditto.
	(*bseti<mode>): Ditto.
	(*bclr<mode>): Ditto.
	(*bclri<mode>): Ditto.
	(*binv<mode>): Ditto.
	(*binvi<mode>): Ditto.
	(*bext<mode>): Ditto.
	(*bexti): Ditto.
	* config/riscv/predicates.md (splittable_const_int_operand):
	Handle bseti.
	(single_bit_mask_operand): New.
	(not_single_bit_mask_operand): Ditto.
	(const31_operand): Ditto.
	(const63_operand): Ditto.
	* config/riscv/riscv.c (riscv_build_integer_1): Handle cost model
	for zbb extension.
	(riscv_output_move): Handle bseti.
	(riscv_print_operand): Handle new operand type: T and S.
	* config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): New.

2021-09-23 Jia-Wei Chen <jiawei@iscas.ac.cn>
	   Shi-Hua Liao <shihua@iscas.ac.cn>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zba-slliuw.c: Apply zbs to this testcase.
	* gcc.target/riscv/zbs-bclr.c: New.
	* gcc.target/riscv/zbs-bext.c: Ditto.
	* gcc.target/riscv/zbs-binv.c: Ditto.
	* gcc.target/riscv/zbs-bset.c: Ditto.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>
Co-authored-by: Shi-Hua Liao <shihua@iscas.ac.cn>
---
 gcc/config/riscv/bitmanip.md                | 102 ++++++++++++++++++++
 gcc/config/riscv/predicates.md              |  22 +++++
 gcc/config/riscv/riscv.c                    |  35 ++++++-
 gcc/config/riscv/riscv.h                    |   8 ++
 gcc/testsuite/gcc.target/riscv/zba-slliuw.c |   4 +-
 gcc/testsuite/gcc.target/riscv/zbs-bclr.c   |  20 ++++
 gcc/testsuite/gcc.target/riscv/zbs-bext.c   |  20 ++++
 gcc/testsuite/gcc.target/riscv/zbs-binv.c   |  20 ++++
 gcc/testsuite/gcc.target/riscv/zbs-bset.c   |  41 ++++++++
 9 files changed, 268 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bext.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-binv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bset.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 4d624514049..59779b48f27 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -40,6 +40,7 @@
 				 (ctz "ctz")
 				 (popcount "cpop")])
 
+(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
 
 ;; ZBA extension.
 
@@ -238,3 +239,104 @@
   "TARGET_ZBB"
   "<bitmanip_insn>\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
+
+;; ZBS extension.
+
+(define_insn "*bset<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(ior:X (ashift:X (const_int 1)
+			 (match_operand:QI 2 "register_operand" "r"))
+	       (match_operand:X 1 "register_operand" "r")))]
+  "TARGET_ZBS"
+  "bset\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bset<mode>_mask"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(ior:X (ashift:X (const_int 1)
+			 (subreg:QI
+			  (and:X (match_operand:X 2 "register_operand" "r")
+				 (match_operand 3 "<X:shiftm1>" "i")) 0))
+	       (match_operand:X 1 "register_operand" "r")))]
+  "TARGET_ZBS"
+  "bset\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bset<mode>_1"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(ashift:X (const_int 1)
+		  (match_operand:QI 1 "register_operand" "r")))]
+  "TARGET_ZBS"
+  "bset\t%0,x0,%1"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bset<mode>_1_mask"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(ashift:X (const_int 1)
+		  (subreg:QI
+		   (and:X (match_operand:X 1 "register_operand" "r")
+			  (match_operand 2 "<X:shiftm1>" "i")) 0)))]
+  "TARGET_ZBS"
+  "bset\t%0,x0,%1"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bseti<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(ior:X (match_operand:X 1 "register_operand" "r")
+	       (match_operand 2 "single_bit_mask_operand" "i")))]
+  "TARGET_ZBS"
+  "bseti\t%0,%1,%S2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bclr<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(and:X (rotate:X (const_int -2)
+			 (match_operand:QI 2 "register_operand" "r"))
+	       (match_operand:X 1 "register_operand" "r")))]
+  "TARGET_ZBS"
+  "bclr\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bclri<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(and:X (match_operand:X 1 "register_operand" "r")
+	       (match_operand 2 "not_single_bit_mask_operand" "i")))]
+  "TARGET_ZBS"
+  "bclri\t%0,%1,%T2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*binv<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(xor:X (ashift:X (const_int 1)
+			 (match_operand:QI 2 "register_operand" "r"))
+	       (match_operand:X 1 "register_operand" "r")))]
+  "TARGET_ZBS"
+  "binv\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*binvi<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(xor:X (match_operand:X 1 "register_operand" "r")
+	       (match_operand 2 "single_bit_mask_operand" "i")))]
+  "TARGET_ZBS"
+  "binvi\t%0,%1,%S2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bext<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(zero_extract:X (match_operand:X 1 "register_operand" "r")
+			(const_int 1)
+			(zero_extend:X
+			 (match_operand:QI 2 "register_operand" "r"))))]
+  "TARGET_ZBS"
+  "bext\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+(define_insn "*bexti"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(zero_extract:X (match_operand:X 1 "register_operand" "r")
+			(const_int 1)
+			(match_operand 2 "immediate_operand" "i")))]
+  "TARGET_ZBS"
+  "bexti\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 23211513554..3da6fd4c049 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -74,6 +74,11 @@
   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
     return false;
 
+  /* Check whether the constant can be loaded in a single
+     instruction with zbs extensions.  */
+  if (TARGET_64BIT && TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
+    return false;
+
   /* Otherwise check whether the constant can be loaded in a single
      instruction.  */
   return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
@@ -217,3 +222,20 @@
 {
   return riscv_gpr_save_operation_p (op);
 })
+
+;; Predicates for the ZBS extension.
+(define_predicate "single_bit_mask_operand"
+  (and (match_code "const_int")
+       (match_test "pow2p_hwi (INTVAL (op))")))
+
+(define_predicate "not_single_bit_mask_operand"
+  (and (match_code "const_int")
+       (match_test "pow2p_hwi (~INTVAL (op))")))
+
+(define_predicate "const31_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) == 31")))
+
+(define_predicate "const63_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) == 63")))
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 66daebbbc8f..77981d8e818 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -409,6 +409,13 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
       codes[0].value = value;
       return 1;
     }
+  if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value))
+    {
+      /* Simply BSETI.  */
+      codes[0].code = UNKNOWN;
+      codes[0].value = value;
+      return 1;
+    }
 
   /* End with ADDI.  When constructing HImode constants, do not generate any
      intermediate value that is not itself a valid HImode constant.  The
@@ -2219,7 +2226,17 @@ riscv_output_move (rtx dest, rtx src)
 	  }
 
       if (src_code == CONST_INT)
-	return "li\t%0,%1";
+	{
+	  if (SMALL_OPERAND (INTVAL (src)) || LUI_OPERAND (INTVAL (src)))
+	    return "li\t%0,%1";
+
+	  if (TARGET_ZBS
+	      && SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
+	    return "bseti\t%0,zero,%S1";
+
+	  /* Should never reach here.  */
+	  abort ();
+	}
 
       if (src_code == HIGH)
 	return "lui\t%0,%h1";
@@ -3560,7 +3577,9 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
    'A'	Print the atomic operation suffix for memory model OP.
    'F'	Print a FENCE if the memory model requires a release.
    'z'	Print x0 if OP is zero, otherwise print OP normally.
-   'i'	Print i if the operand is not a register.  */
+   'i'	Print i if the operand is not a register.
+   'S'	Print shift-index of single-bit mask OP.
+   'T'	Print shift-index of inverted single-bit mask OP.  */
 
 static void
 riscv_print_operand (FILE *file, rtx op, int letter)
@@ -3600,6 +3619,18 @@ riscv_print_operand (FILE *file, rtx op, int letter)
         fputs ("i", file);
       break;
 
+    case 'S':
+      {
+	rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
+	output_addr_const (file, newop);
+	break;
+      }
+    case 'T':
+      {
+	rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
+	output_addr_const (file, newop);
+	break;
+      }
     default:
       switch (code)
 	{
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index f47d5b40a66..64287124735 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -526,6 +526,14 @@ enum reg_class
   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)	\
    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 
+/* If this is a single bit mask, then we can load it with bseti.  But this
+   is not useful for any of the low 31 bits because we can use addi or lui
+   to load them.  It is wrong for loading SImode 0x80000000 on rv64 because it
+   needs to be sign-extended.  So we restrict this to the upper 32-bits
+   only.  */
+#define SINGLE_BIT_MASK_OPERAND(VALUE) \
+  (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
+
 /* Stack layout; function entry, exit and calling.  */
 
 #define STACK_GROWS_DOWNWARD 1
diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
index 50399f68e08..a7a3dc77d53 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
 
 long
 foo (long i)
@@ -8,4 +8,4 @@ foo (long i)
 }
 /* XXX: This pattern need combine improvement or intermediate instruction
  *      from zbs.   */
-/* { dg-final { scan-assembler-not "slli.uw" } } */
+/* { dg-final { scan-assembler "slli.uw" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
new file mode 100644
index 00000000000..4a3c2f1cdaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+
+/* bclr */
+long
+foo0 (long i, long j)
+{
+  return i & ~(1L << j);
+}
+
+/* bclri */
+long
+foo1 (long i)
+{
+  return i & ~(1L << 20);
+}
+
+/* { dg-final { scan-assembler-times "bclr\t" 1 } } */
+/* { dg-final { scan-assembler-times "bclri\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
new file mode 100644
index 00000000000..a093cdc8d1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+
+/* bext */
+long
+foo0 (long i, long j)
+{
+  return 1L & (i >> j);
+}
+
+/* bexti */
+long
+foo1 (long i)
+{
+  return 1L & (i >> 20);
+}
+
+/* { dg-final { scan-assembler-times "bexti\t" 1 } } */
+/* { dg-final { scan-assembler-times "bext\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-binv.c b/gcc/testsuite/gcc.target/riscv/zbs-binv.c
new file mode 100644
index 00000000000..e4e48b9cdfd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-binv.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+
+/* binv */
+long
+foo0 (long i, long j)
+{
+  return i ^ (1L << j);
+}
+
+/* binvi */
+long
+foo1 (long i)
+{
+  return i ^ (1L << 20);
+}
+
+/* { dg-final { scan-assembler-times "binv\t" 1 } } */
+/* { dg-final { scan-assembler-times "binvi\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bset.c b/gcc/testsuite/gcc.target/riscv/zbs-bset.c
new file mode 100644
index 00000000000..733d4279d3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bset.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+
+/* bset */
+long
+sub0 (long i, long j)
+{
+  return i | (1L << j);
+}
+
+/* bset_mask */
+long
+sub1 (long i, long j)
+{
+  return i | (1L << (j & 0x3f));
+}
+
+/* bset_1 */
+long
+sub2 (long i)
+{
+  return 1L << i;
+}
+
+/* bset_1_mask */
+long
+sub3 (long i)
+{
+  return 1L << (i & 0x3f);
+}
+
+/* bseti */
+long
+sub4 (long i)
+{
+  return i | (1L << 20);
+}
+
+/* { dg-final { scan-assembler-times "bset\t" 4 } } */
+/* { dg-final { scan-assembler-times "bseti\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
-- 
2.33.0

[RFC PATCH 8/8] RISC-V: Cost model for ZBS extension.

[Kito Cheng]

2021-09-23 Kito Cheng <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_rtx_costs): Handle cost model
	for zbs extension.
---
 gcc/config/riscv/riscv.c | 47 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 77981d8e818..055111ac30c 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1851,6 +1851,24 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	    *total = COSTS_N_INSNS (1);
 	    return true;
 	}
+      /* bclri pattern for zbs.  */
+      if (TARGET_ZBS
+	  && not_single_bit_mask_operand (XEXP (x, 1), VOIDmode))
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      /* bclr pattern for zbs.  */
+      if (TARGET_ZBS
+	  && REG_P (XEXP (x, 1))
+	  && GET_CODE (XEXP (x, 0)) == ROTATE
+	  && CONST_INT_P (XEXP ((XEXP (x, 0)), 0))
+	  && INTVAL (XEXP ((XEXP (x, 0)), 0)) == -2)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+
       gcc_fallthrough ();
     case IOR:
     case XOR:
@@ -1861,6 +1879,18 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	  *total = riscv_binary_cost (x, 1, 2);
 	  return true;
 	}
+
+      /* bset[i] and binv[i] pattern for zbs.  */
+      if ((GET_CODE (x) == IOR || GET_CODE (x) == XOR)
+	  && TARGET_ZBS
+	  && ((GET_CODE (XEXP (x, 0)) == ASHIFT
+	      && CONST_INT_P (XEXP (XEXP (x, 0), 0)))
+	      || single_bit_mask_operand (XEXP (x, 1), VOIDmode)))
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+
       /* Double-word operations use two single-word operations.  */
       *total = riscv_binary_cost (x, 1, 2);
       return false;
@@ -1876,9 +1906,26 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
 	  return true;
 	}
+      /* bext pattern for zbs.  */
+      if (TARGET_ZBS && outer_code == SET
+	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && INTVAL (XEXP (x, 1)) == 1)
+	{
+	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
+	  return true;
+	}
       return false;
 
     case ASHIFT:
+      /* bset pattern for zbs.  */
+      if (TARGET_ZBS
+	  && CONST_INT_P (XEXP (x, 0))
+	  && INTVAL (XEXP (x, 0)) == 1)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      gcc_fallthrough ();
     case ASHIFTRT:
     case LSHIFTRT:
       *total = riscv_binary_cost (x, SINGLE_SHIFT_COST,
-- 
2.33.0

Re: [RFC PATCH 1/8] RISC-V: Minimal support of bitmanip extension

[Christoph Muellner]

Hi Kito,

On Thu, Sep 23, 2021 at 9:57 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> 2021-09-23  Kito Cheng  <kito.cheng@sifive.com>
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.c (riscv_ext_version_table):
>         Add zba, zbb, zbc and zbs.
>         (riscv_ext_flag_table): Ditto.
>         * config/riscv/riscv-opts.h (MASK_ZBA): New.
>         (MASK_ZBB): Ditto.
>         (MASK_ZBC): Ditto.
>         (MASK_ZBS): Ditto.
>         (TARGET_ZBA): Ditto.
>         (TARGET_ZBB): Ditto.
>         (TARGET_ZBC): Ditto.
>         (TARGET_ZBS): Ditto.
>         * config/riscv/riscv.opt (riscv_zb_subext): New.
> ---
>  gcc/common/config/riscv/riscv-common.c | 10 ++++++++++
>  gcc/config/riscv/riscv-opts.h          | 10 ++++++++++
>  gcc/config/riscv/riscv.opt             |  3 +++
>  3 files changed, 23 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
> index 10868fd417d..37b6ea80086 100644
> --- a/gcc/common/config/riscv/riscv-common.c
> +++ b/gcc/common/config/riscv/riscv-common.c
> @@ -101,6 +101,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
>    {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
>
> +  {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},

I think this needs another specification class (there is a
specification for the instructions and it is in public review).
Proposal: ISA_SPEC_CLASS_FROZEN_2021

BR
Christoph

> +
>    /* Terminate the list.  */
>    {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
>  };
> @@ -906,6 +911,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>
> +  {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
> +  {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> +  {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
> +  {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
> +
>    {NULL, NULL, 0}
>  };
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index f4cf6ca4b82..2efc4b80f1f 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -73,4 +73,14 @@ enum stack_protector_guard {
>  #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
>  #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>
> +#define MASK_ZBA      (1 << 0)
> +#define MASK_ZBB      (1 << 1)
> +#define MASK_ZBC      (1 << 2)
> +#define MASK_ZBS      (1 << 3)
> +
> +#define TARGET_ZBA    ((riscv_zb_subext & MASK_ZBA) != 0)
> +#define TARGET_ZBB    ((riscv_zb_subext & MASK_ZBB) != 0)
> +#define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
> +#define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
> +
>  #endif /* ! GCC_RISCV_OPTS_H */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 5ff85c21430..15bf89e17c2 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
>  TargetVariable
>  int riscv_zi_subext
>
> +TargetVariable
> +int riscv_zb_subext
> +
>  Enum
>  Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>  Supported ISA specs (for use with the -misa-spec= option):
> --
> 2.33.0
>

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Christoph Muellner]

In case somebody wants to test this patchset, a patchset for Binutils
is required as well.
AFAIK here would be the Binutils branch with the required changes:
https://github.com/riscv-collab/riscv-binutils-gdb/tree/riscv-binutils-experiment

On Thu, Sep 23, 2021 at 9:57 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> Bit manipulation extension[1] is finishing the public review and waiting for
> the rest of the ratification process, I believe that will become a ratified
> extension soon, so I think it's time to submit to upstream for review now :)
>
> As the title included RFC, it's not a rush to merge to trunk yet, I would
> like to merge that until it is officially ratified.
>
> This patch set is the implementation of bit-manipulation extension, which
> includes zba, zbb, zbc and zbs extension, but only included in instruction/md
> pattern only, no intrinsic function implementation.
>
> Most work is done by Jim Willson and many other contributors
> on https://github.com/riscv-collab/riscv-gcc.
>
>
> [1] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
>
>

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Jim Wilson]

On Thu, Sep 23, 2021 at 12:57 AM Kito Cheng <kito.cheng@sifive.com> wrote:

> Bit manipulation extension[1] is finishing the public review and waiting
> for
> the rest of the ratification process, I believe that will become a ratified
> extension soon, so I think it's time to submit to upstream for review now
> :)
>

We still don't have upstream zbs assembler support.  We have rejected other
patches because they didn't upstream the assembler support first.  We
should be following the same rule here for bitmanip.

Maybe we can ask PLCT to write the missing assembler support?

Jim

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Jim Wilson]

On Mon, Sep 27, 2021 at 4:20 AM Christoph Muellner <
cmuellner@ventanamicro.com> wrote:

> In case somebody wants to test this patchset, a patchset for Binutils
> is required as well.
> AFAIK here would be the Binutils branch with the required changes:
>
> https://github.com/riscv-collab/riscv-binutils-gdb/tree/riscv-binutils-experiment


This branch only has the zba/zbb/zbc support that is already upstream.
There is nothing useful here.

Jim

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Christoph Muellner]

On Wed, Sep 29, 2021 at 12:01 AM Jim Wilson <jimw@sifive.com> wrote:
>
> On Thu, Sep 23, 2021 at 12:57 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>>
>> Bit manipulation extension[1] is finishing the public review and waiting for
>> the rest of the ratification process, I believe that will become a ratified
>> extension soon, so I think it's time to submit to upstream for review now :)
>
>
> We still don't have upstream zbs assembler support.  We have rejected other patches because they didn't upstream the assembler support first.  We should be following the same rule here for bitmanip.
>
> Maybe we can ask PLCT to write the missing assembler support?

We talked about this in the T&R meeting on Monday.
Philipp Tomsich mentioned, that he has a patchset from earlier this
year, which adds support for Zbs.
He proposed to rebase it and send it to the list in the next days.

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Jim Wilson]

On Tue, Sep 28, 2021 at 3:05 PM Christoph Muellner <
cmuellner@ventanamicro.com> wrote:

> We talked about this in the T&R meeting on Monday.
> Philipp Tomsich mentioned, that he has a patchset from earlier this
> year, which adds support for Zbs.
> He proposed to rebase it and send it to the list in the next days.
>

And this is hopefully a patch that isn't contaminated by any of the changes
from Claire that we can't use.  That is one of the benefits of asking PLCT
as they never worked with Claire.  But at this point I think that enough
time has passed and enough changes were made to the zbs spec, and
considering that there is really only one good way to implement the zbs
binutils support anyways, I think we are probably safe to use patches from
one of us that did work with Claire.

Jim

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Vineet Gupta]

Hi Kito,

On 9/23/21 12:57 AM, Kito Cheng wrote:
> Bit manipulation extension[1] is finishing the public review and waiting for
> the rest of the ratification process, I believe that will become a ratified
> extension soon, so I think it's time to submit to upstream for review now :)
> 
> As the title included RFC, it's not a rush to merge to trunk yet, I would
> like to merge that until it is officially ratified.
> 
> This patch set is the implementation of bit-manipulation extension, which
> includes zba, zbb, zbc and zbs extension, but only included in instruction/md
> pattern only, no intrinsic function implementation.
> 
> Most work is done by Jim Willson and many other contributors
> on https://github.com/riscv-collab/riscv-gcc.
> 
> 
> [1] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0

I wanted to give these a try. Is it reasonable to apply these to a gcc 
11.1 baseline and give a spin in buildroot or do these absolutely have 
to be bleeding edge gcc.

Thx,
-Vineet

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Kito Cheng]

Hi Vineet:

I am not familiar with buildroot, so I am not sure which GCC version will work,
but I think the patch set should be able to apply both gcc 11.1 and
trunk without conflict.

Here is a gcc 11.1 + this patch set on my github, hope this could help :)
https://github.com/kito-cheng/riscv-gcc/tree/riscv-gcc-11.1.0-zbabcs

On Thu, Oct 14, 2021 at 4:22 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
>
> Hi Kito,
>
> On 9/23/21 12:57 AM, Kito Cheng wrote:
> > Bit manipulation extension[1] is finishing the public review and waiting for
> > the rest of the ratification process, I believe that will become a ratified
> > extension soon, so I think it's time to submit to upstream for review now :)
> >
> > As the title included RFC, it's not a rush to merge to trunk yet, I would
> > like to merge that until it is officially ratified.
> >
> > This patch set is the implementation of bit-manipulation extension, which
> > includes zba, zbb, zbc and zbs extension, but only included in instruction/md
> > pattern only, no intrinsic function implementation.
> >
> > Most work is done by Jim Willson and many other contributors
> > on https://github.com/riscv-collab/riscv-gcc.
> >
> >
> > [1] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
>
> I wanted to give these a try. Is it reasonable to apply these to a gcc
> 11.1 baseline and give a spin in buildroot or do these absolutely have
> to be bleeding edge gcc.
>
> Thx,
> -Vineet

Re: [RFC PATCH 1/8] RISC-V: Minimal support of bitmanip extension

[Kito Cheng]

Hi Christoph:

> I think this needs another specification class (there is a
> specification for the instructions and it is in public review).
> Proposal: ISA_SPEC_CLASS_FROZEN_2021

That's a good point, but ISA_SPEC_CLASS_FROZEN_2021 is hard to
reference to which spec, so I would prefer to add a -misa-spec=2021 to
align platform/profile spec, and then ISA_SPEC_CLASS_2021, and before
RISC-V platform/profile spec has released, let keep
ISA_SPEC_CLASS_NONE :p

> BR
> Christoph

Re: [RFC PATCH 1/8] RISC-V: Minimal support of bitmanip extension

[Christoph Muellner]

On Mon, Oct 18, 2021 at 10:48 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> Hi Christoph:
>
> > I think this needs another specification class (there is a
> > specification for the instructions and it is in public review).
> > Proposal: ISA_SPEC_CLASS_FROZEN_2021
>
> That's a good point, but ISA_SPEC_CLASS_FROZEN_2021 is hard to
> reference to which spec, so I would prefer to add a -misa-spec=2021 to
> align platform/profile spec, and then ISA_SPEC_CLASS_2021, and before
> RISC-V platform/profile spec has released, let keep
> ISA_SPEC_CLASS_NONE :p

For sure we cannot reference a spec that is not frozen yet (i.e.
platform/profile).
ISA_SPEC_CLASS_FROZEN_2021 was a proposal for all groups of ISA extensions
that have been frozen in 2021 (zb*, zk*, etc.) and will eventually be ratified.
But yes, keeping NONE until the specifications are ratified and change
the specification
class then is also possible.

Re: [RFC PATCH 1/8] RISC-V: Minimal support of bitmanip extension

[Kito Cheng]

> > That's a good point, but ISA_SPEC_CLASS_FROZEN_2021 is hard to
> > reference to which spec, so I would prefer to add a -misa-spec=2021 to
> > align platform/profile spec, and then ISA_SPEC_CLASS_2021, and before
> > RISC-V platform/profile spec has released, let keep
> > ISA_SPEC_CLASS_NONE :p
>
> For sure we cannot reference a spec that is not frozen yet (i.e.
> platform/profile).
> ISA_SPEC_CLASS_FROZEN_2021 was a proposal for all groups of ISA extensions
> that have been frozen in 2021 (zb*, zk*, etc.) and will eventually be ratified.
> But yes, keeping NONE until the specifications are ratified and change
> the specification
> class then is also possible.

I expect those specs can be ratified at the end of this year, and then
we still have a few months
to update before GCC 12 release.

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

[Kito Cheng]

As we discussed in the last RISC-V GNU sync up, I've committed this
patch-set to trunk after rebase and running regression with latest
binutils.

On Mon, Oct 18, 2021 at 11:23 AM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> Hi Vineet:
>
> I am not familiar with buildroot, so I am not sure which GCC version will work,
> but I think the patch set should be able to apply both gcc 11.1 and
> trunk without conflict.
>
> Here is a gcc 11.1 + this patch set on my github, hope this could help :)
> https://github.com/kito-cheng/riscv-gcc/tree/riscv-gcc-11.1.0-zbabcs
>
> On Thu, Oct 14, 2021 at 4:22 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
> >
> > Hi Kito,
> >
> > On 9/23/21 12:57 AM, Kito Cheng wrote:
> > > Bit manipulation extension[1] is finishing the public review and waiting for
> > > the rest of the ratification process, I believe that will become a ratified
> > > extension soon, so I think it's time to submit to upstream for review now :)
> > >
> > > As the title included RFC, it's not a rush to merge to trunk yet, I would
> > > like to merge that until it is officially ratified.
> > >
> > > This patch set is the implementation of bit-manipulation extension, which
> > > includes zba, zbb, zbc and zbs extension, but only included in instruction/md
> > > pattern only, no intrinsic function implementation.
> > >
> > > Most work is done by Jim Willson and many other contributors
> > > on https://github.com/riscv-collab/riscv-gcc.
> > >
> > >
> > > [1] https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
> >
> > I wanted to give these a try. Is it reasonable to apply these to a gcc
> > 11.1 baseline and give a spin in buildroot or do these absolutely have
> > to be bleeding edge gcc.
> >
> > Thx,
> > -Vineet