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From: Kito Cheng <kito.cheng@gmail.com>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: 钟居哲 <juzhe.zhong@rivai.ai>,
	"cooper.joshua" <cooper.joshua@linux.alibaba.com>,
	gcc-patches <gcc-patches@gcc.gnu.org>,
	"jim.wilson.gcc" <jim.wilson.gcc@gmail.com>,
	palmer <palmer@dabbelt.com>, andrew <andrew@sifive.com>,
	"philipp.tomsich" <philipp.tomsich@vrull.eu>,
	"Christoph Müllner" <christoph.muellner@vrull.eu>,
	jinma <jinma@linux.alibaba.com>,
	"Cooper Qu" <cooper.qu@linux.alibaba.com>
Subject: Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
Date: Thu, 21 Dec 2023 17:43:49 +0800	[thread overview]
Message-ID: <CA+yXCZC5EVeHYpp-aa2_pc8WKF0CUAqV9zggxBPTQmt0fxWmbQ@mail.gmail.com> (raw)
In-Reply-To: <60201857-c9c2-4e20-a79d-cc4bdbfb17bb@gmail.com>

Why not just check the prefix is 'v'? I don't think xtheadvector able
to work with other vector stuffs like vector crypto or any other new
vector stuffs, then we don't need extra attribute.

On Thu, Dec 21, 2023 at 12:42 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 12/20/23 15:48, 钟居哲 wrote:
> >  >> So rather than looking at the mode, would it make more sense to have an
> >>>attribute (or re-use an existing attribute) to identify which opcodes
> >>>are going to need prefixing?  We've got access to the INSN via
> >>>current_output_insn.  So we can lookup attributes trivially.
> >
> > Yes, I totally aggree with Jeff's idea. We have addes many attributes
> > for each RVV instructions.
> > For example, VSETVL PASS is highly depending on those attribute to do
> > the optimizations.
> Also note that with attributes, we can potentially even deal with cases
> where some alternatives need special handling while other alternatives
> simply aren't available with the thead extension.  Not sure if that's
> going to be needed or not, but it's worth remembering.
>
> Jeff

  reply	other threads:[~2023-12-21  9:44 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-18  4:22 [PATCH v2 0/9] RISC-V: Support XTheadVector extensions Jun Sha (Joshua)
2023-11-18  4:26 ` [PATCH v2 1/9] RISC-V: minimal support for xtheadvector Jun Sha (Joshua)
2023-11-18 10:06   ` Kito Cheng
2023-11-18  4:28 ` [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector Jun Sha (Joshua)
2023-11-18 10:13   ` Kito Cheng
2023-11-18  4:29 ` [PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) Jun Sha (Joshua)
2023-11-18  4:32 ` [PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) Jun Sha (Joshua)
2023-11-18  4:34 ` [PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) Jun Sha (Joshua)
2023-11-18  4:35 ` [PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) Jun Sha (Joshua)
2023-11-18  4:37 ` [PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics Jun Sha (Joshua)
2023-11-18  4:39 ` [PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension Jun Sha (Joshua)
2023-12-20 12:20 ` [PATCH v3 0/6] RISC-V: Support " Jun Sha (Joshua)
2023-12-20 12:25   ` [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-20 18:14     ` Jeff Law
2023-12-27  2:46       ` 回复:[PATCH " joshua
2023-12-29  1:44       ` joshua
2023-12-20 12:27   ` [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns Jun Sha (Joshua)
2023-12-20 18:16     ` Jeff Law
2023-12-27  2:49       ` 回复:[PATCH " joshua
2023-12-28 15:50         ` Jeff Law
2023-12-20 12:30   ` [PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2023-12-20 12:32   ` [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-20 18:22     ` Jeff Law
2023-12-20 22:48       ` 钟居哲
2023-12-21  4:41         ` Jeff Law
2023-12-21  9:43           ` Kito Cheng [this message]
2023-12-25  6:25     ` [PATCH v4 " Jun Sha (Joshua)
2023-12-25  6:37       ` juzhe.zhong
2023-12-25  7:08         ` 回复:[PATCH " joshua
2023-12-25  7:09           ` juzhe.zhong
2023-12-25  8:14       ` [PATCH " Jun Sha (Joshua)
2023-12-25  8:18         ` juzhe.zhong
2023-12-20 12:34   ` [PATCH v3 5/6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2023-12-20 14:00     ` 钟居哲
2023-12-20 14:24       ` 回复:[PATCH " joshua
2023-12-20 14:27         ` 钟居哲
2023-12-20 14:41           ` 回复:回复:[PATCH " joshua
2023-12-20 14:48             ` 回复:[PATCH " 钟居哲
2023-12-20 14:55             ` 钟居哲
2023-12-20 15:21               ` 回复:回复:[PATCH " joshua
2023-12-20 15:29                 ` 回复:[PATCH " 钟居哲
2023-12-25  6:29     ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29  1:46       ` Jun Sha (Joshua)
2023-12-29  1:58         ` juzhe.zhong
2023-12-29  2:09           ` 回复:[PATCH " joshua
2023-12-29  2:11             ` Re:[PATCH " joshua
2023-12-29  2:14             ` 回复:[PATCH " juzhe.zhong
2023-12-29  2:17               ` Re:[PATCH " joshua
2023-12-29  2:22                 ` juzhe.zhong
2023-12-29  2:25                   ` Re:Re:[PATCH " joshua
2023-12-29  2:25                     ` Re:[PATCH " juzhe.zhong
2023-12-29  2:30                       ` joshua
2023-12-29  2:31                         ` juzhe.zhong
2023-12-29  2:47                         ` juzhe.zhong
2023-12-20 12:36   ` [PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2023-12-25  6:31     ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29  1:49       ` Jun Sha (Joshua)
2023-12-20 23:04   ` [PATCH v3 0/6] RISC-V: Support XTheadVector extension 钟居哲
2023-12-22  3:33     ` 回复:[PATCH " joshua
2023-12-22  8:07       ` juzhe.zhong
2023-12-22 10:29         ` 回复:回复:[PATCH " joshua
2023-12-22 10:31           ` 回复:[PATCH " juzhe.zhong
2023-12-23  3:37             ` 回复:回复:[PATCH " joshua
2023-12-23 22:52               ` 回复:[PATCH " 钟居哲
2023-12-22 17:21         ` Jeff Law
2023-12-20 23:08   ` [PATCH " 钟居哲
2023-12-21  3:28     ` Jeff Law
2023-12-21  3:30       ` juzhe.zhong
2023-12-21  4:04         ` Jeff Law

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