From: Kito Cheng <kito.cheng@gmail.com>
To: Mary Bennett <mary.bennett@embecosm.com>
Cc: gcc-patches@gcc.gnu.org, rep.dot.nop@gmail.com
Subject: Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
Date: Tue, 10 Oct 2023 07:52:12 -0700 [thread overview]
Message-ID: <CA+yXCZC8DK0vFKUGeO2+5d+n_oj_5Ufcz0tp-UTxPTNgyCmWcQ@mail.gmail.com> (raw)
In-Reply-To: <20230930120038.3110583-1-mary.bennett@embecosm.com>
Just repeat what I said on the mailing list again :P it's LGTM, just
need to rebase to deal with riscv.opt related changes :)
On Sat, Sep 30, 2023 at 8:02 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> Thank you for reviewing this patch.
>
> v1->v2:
> * Add XCValu RTL.
> * Change assembly mnemonics from mixed case to lower case.
>
> v2->v3:
> * Change commit message from past tense to present.
> * Add documentation for new dg-effective-targets.
>
> This patch series presents the comprehensive implementation of the MAC and ALU
> extension for CORE-V.
>
> Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> ensure its correctness and compatibility with the existing codebase.
> However, your input, reviews, and suggestions are invaluable in making this
> extension even more robust.
>
> The CORE-V builtins are described in the specification [1] and work can be
> found in the OpenHW group's Github repository [2].
>
> [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> [2] github.com/openhwgroup/corev-gcc
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> RISC-V: Add support for XCValu extension in CV32E40P
> RISC-V: Add support for XCVmac extension in CV32E40P
>
> gcc/common/config/riscv/riscv-common.cc | 6 +
> gcc/config/riscv/constraints.md | 7 +
> gcc/config/riscv/corev.def | 43 ++
> gcc/config/riscv/corev.md | 693 ++++++++++++++++++
> gcc/config/riscv/predicates.md | 5 +
> gcc/config/riscv/riscv-builtins.cc | 13 +
> gcc/config/riscv/riscv-ftypes.def | 11 +
> gcc/config/riscv/riscv-opts.h | 7 +
> gcc/config/riscv/riscv.cc | 7 +
> gcc/config/riscv/riscv.md | 1 +
> gcc/config/riscv/riscv.opt | 3 +
> gcc/doc/extend.texi | 174 +++++
> gcc/doc/sourcebuild.texi | 12 +
> .../gcc.target/riscv/cv-alu-compile.c | 252 +++++++
> .../riscv/cv-alu-fail-compile-addn.c | 11 +
> .../riscv/cv-alu-fail-compile-addrn.c | 11 +
> .../riscv/cv-alu-fail-compile-addun.c | 11 +
> .../riscv/cv-alu-fail-compile-addurn.c | 11 +
> .../riscv/cv-alu-fail-compile-clip.c | 11 +
> .../riscv/cv-alu-fail-compile-clipu.c | 11 +
> .../riscv/cv-alu-fail-compile-subn.c | 11 +
> .../riscv/cv-alu-fail-compile-subrn.c | 11 +
> .../riscv/cv-alu-fail-compile-subun.c | 11 +
> .../riscv/cv-alu-fail-compile-suburn.c | 11 +
> .../gcc.target/riscv/cv-alu-fail-compile.c | 32 +
> .../gcc.target/riscv/cv-mac-compile.c | 198 +++++
> .../riscv/cv-mac-fail-compile-mac.c | 25 +
> .../riscv/cv-mac-fail-compile-machhsn.c | 24 +
> .../riscv/cv-mac-fail-compile-machhsrn.c | 24 +
> .../riscv/cv-mac-fail-compile-machhun.c | 24 +
> .../riscv/cv-mac-fail-compile-machhurn.c | 24 +
> .../riscv/cv-mac-fail-compile-macsn.c | 24 +
> .../riscv/cv-mac-fail-compile-macsrn.c | 24 +
> .../riscv/cv-mac-fail-compile-macun.c | 24 +
> .../riscv/cv-mac-fail-compile-macurn.c | 24 +
> .../riscv/cv-mac-fail-compile-msu.c | 25 +
> .../riscv/cv-mac-fail-compile-mulhhsn.c | 24 +
> .../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 +
> .../riscv/cv-mac-fail-compile-mulhhun.c | 24 +
> .../riscv/cv-mac-fail-compile-mulhhurn.c | 24 +
> .../riscv/cv-mac-fail-compile-mulsn.c | 24 +
> .../riscv/cv-mac-fail-compile-mulsrn.c | 24 +
> .../riscv/cv-mac-fail-compile-mulun.c | 24 +
> .../riscv/cv-mac-fail-compile-mulurn.c | 24 +
> .../riscv/cv-mac-test-autogeneration.c | 18 +
> gcc/testsuite/lib/target-supports.exp | 26 +
> 46 files changed, 2052 insertions(+)
> create mode 100644 gcc/config/riscv/corev.def
> create mode 100644 gcc/config/riscv/corev.md
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhun.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsrn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulun.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulurn.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogeneration.c
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-10-10 14:52 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 15:07 [PATCH " Mary Bennett
2023-09-19 15:07 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-19 15:07 ` [PATCH 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-09-23 9:04 ` Kito Cheng
2023-09-27 12:26 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-09-27 12:26 ` [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-27 12:26 ` [PATCH v2 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-09-30 12:00 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-09-30 12:00 ` [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-30 12:00 ` [PATCH v3 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-10-10 14:52 ` Kito Cheng [this message]
2023-10-11 12:06 ` [PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-10-11 12:06 ` [PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-10-11 12:06 ` [PATCH v4 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-10-11 13:49 ` [PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Jeff Law
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