From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa31.google.com (mail-vk1-xa31.google.com [IPv6:2607:f8b0:4864:20::a31]) by sourceware.org (Postfix) with ESMTPS id 251703858D28 for ; Tue, 10 Oct 2023 14:52:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 251703858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa31.google.com with SMTP id 71dfb90a1353d-49dd647a477so2086484e0c.3 for ; Tue, 10 Oct 2023 07:52:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696949543; x=1697554343; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=1Psu3ckPwwOrxgV8alhHC3x5o+XMEu8LdQYLdDURQyw=; b=cE9iXIokykvtr+U4Bxl26LjMRLzim6NhEoUCgiW1aMxCQfE+ns+z9sfRNnjzVYUiWo ISWGjkO/mF1eMD9kzl1fGiijVIe3mMnLNXzIDgH1N6wYD5R1M7rfTDBVepi0gmDvd0qr QEUU5wAvQHLHD/HrU8nbWAAt0vtQLoTT9rv5pm4BvMMkCaZbhOfr5aLxu2dP2U30Hb9y 9jUToEPURMFtJfit6HTWWBVNUrN9WkaO3cTBjaBvblaTle6YRILkG6BWDcF34fCs32Uc r+NYwiMJK1YWLezoR5kFgz4h3YSnDIaomOYYtPNVvlN9OljGvOIl9/drpVQLkAH/vfwE YLyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696949543; x=1697554343; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Psu3ckPwwOrxgV8alhHC3x5o+XMEu8LdQYLdDURQyw=; b=tnJQPu8uoGJBEUFi2hTyLmUCrn0W8ObLViD+L7VeNUWSDY3Tn9RFE5T/uh5jdcTJ4I 2bJi+qP3HUN0EATAekJQTafxcisofaicqQRG+KCyEhskUN++kNn0+B7vkutOs2NWpuMR 4q/TQCwVGmTUSas8jxbN/6pzmO0duQqxDXGhLakl7IapaNvBjWDb45V/fEHR0TrDgrVi b3Zbr4iivkPngR29ExNLH7QXdZikwQza6+2M6OIRoMUUgRI0WfWuR7D1m8ndwmz55ugv fQz5K6XnJ4RQQtiTXSy4ck3DgVedHA/1HUGGbOkmzVLu3ShZ0DbpIHFnsfWst+C8Sp8l fvAQ== X-Gm-Message-State: AOJu0YyT8d7QHJ4lU10fEBs/KxzbNLm8z++0oQqPJbaozDIXTvtKnxmo 2LFRKhvLxIsC3NxBDwcsEflrkQy+uoOrSKx3bOI= X-Google-Smtp-Source: AGHT+IELSaC04sPEbp5B3l4M9FlqU4uL1nHEgaW3cNuw6bZ/M50L7LndX6qKJiWxIEM5aXFafxDx4nCEnnDC3a976Nc= X-Received: by 2002:a1f:e744:0:b0:499:696c:7810 with SMTP id e65-20020a1fe744000000b00499696c7810mr14662921vkh.0.1696949543248; Tue, 10 Oct 2023 07:52:23 -0700 (PDT) MIME-Version: 1.0 References: <20230927122626.775649-1-mary.bennett@embecosm.com> <20230930120038.3110583-1-mary.bennett@embecosm.com> In-Reply-To: <20230930120038.3110583-1-mary.bennett@embecosm.com> From: Kito Cheng Date: Tue, 10 Oct 2023 07:52:12 -0700 Message-ID: Subject: Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions To: Mary Bennett Cc: gcc-patches@gcc.gnu.org, rep.dot.nop@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Just repeat what I said on the mailing list again :P it's LGTM, just need to rebase to deal with riscv.opt related changes :) On Sat, Sep 30, 2023 at 8:02=E2=80=AFPM Mary Bennett wrote: > > Thank you for reviewing this patch. > > v1->v2: > * Add XCValu RTL. > * Change assembly mnemonics from mixed case to lower case. > > v2->v3: > * Change commit message from past tense to present. > * Add documentation for new dg-effective-targets. > > This patch series presents the comprehensive implementation of the MAC an= d ALU > extension for CORE-V. > > Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites t= o > ensure its correctness and compatibility with the existing codebase. > However, your input, reviews, and suggestions are invaluable in making th= is > extension even more robust. > > The CORE-V builtins are described in the specification [1] and work can b= e > found in the OpenHW group's Github repository [2]. > > [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-bui= ltin-spec.md > > [2] github.com/openhwgroup/corev-gcc > > Contributors: > Mary Bennett > Nandni Jamnadas > Pietra Ferreira > Charlie Keaney > Jessica Mills > Craig Blackmore > Simon Cook > Jeremy Bennett > Helene Chelin > > RISC-V: Add support for XCValu extension in CV32E40P > RISC-V: Add support for XCVmac extension in CV32E40P > > gcc/common/config/riscv/riscv-common.cc | 6 + > gcc/config/riscv/constraints.md | 7 + > gcc/config/riscv/corev.def | 43 ++ > gcc/config/riscv/corev.md | 693 ++++++++++++++++++ > gcc/config/riscv/predicates.md | 5 + > gcc/config/riscv/riscv-builtins.cc | 13 + > gcc/config/riscv/riscv-ftypes.def | 11 + > gcc/config/riscv/riscv-opts.h | 7 + > gcc/config/riscv/riscv.cc | 7 + > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/riscv.opt | 3 + > gcc/doc/extend.texi | 174 +++++ > gcc/doc/sourcebuild.texi | 12 + > .../gcc.target/riscv/cv-alu-compile.c | 252 +++++++ > .../riscv/cv-alu-fail-compile-addn.c | 11 + > .../riscv/cv-alu-fail-compile-addrn.c | 11 + > .../riscv/cv-alu-fail-compile-addun.c | 11 + > .../riscv/cv-alu-fail-compile-addurn.c | 11 + > .../riscv/cv-alu-fail-compile-clip.c | 11 + > .../riscv/cv-alu-fail-compile-clipu.c | 11 + > .../riscv/cv-alu-fail-compile-subn.c | 11 + > .../riscv/cv-alu-fail-compile-subrn.c | 11 + > .../riscv/cv-alu-fail-compile-subun.c | 11 + > .../riscv/cv-alu-fail-compile-suburn.c | 11 + > .../gcc.target/riscv/cv-alu-fail-compile.c | 32 + > .../gcc.target/riscv/cv-mac-compile.c | 198 +++++ > .../riscv/cv-mac-fail-compile-mac.c | 25 + > .../riscv/cv-mac-fail-compile-machhsn.c | 24 + > .../riscv/cv-mac-fail-compile-machhsrn.c | 24 + > .../riscv/cv-mac-fail-compile-machhun.c | 24 + > .../riscv/cv-mac-fail-compile-machhurn.c | 24 + > .../riscv/cv-mac-fail-compile-macsn.c | 24 + > .../riscv/cv-mac-fail-compile-macsrn.c | 24 + > .../riscv/cv-mac-fail-compile-macun.c | 24 + > .../riscv/cv-mac-fail-compile-macurn.c | 24 + > .../riscv/cv-mac-fail-compile-msu.c | 25 + > .../riscv/cv-mac-fail-compile-mulhhsn.c | 24 + > .../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 + > .../riscv/cv-mac-fail-compile-mulhhun.c | 24 + > .../riscv/cv-mac-fail-compile-mulhhurn.c | 24 + > .../riscv/cv-mac-fail-compile-mulsn.c | 24 + > .../riscv/cv-mac-fail-compile-mulsrn.c | 24 + > .../riscv/cv-mac-fail-compile-mulun.c | 24 + > .../riscv/cv-mac-fail-compile-mulurn.c | 24 + > .../riscv/cv-mac-test-autogeneration.c | 18 + > gcc/testsuite/lib/target-supports.exp | 26 + > 46 files changed, 2052 insertions(+) > create mode 100644 gcc/config/riscv/corev.def > create mode 100644 gcc/config/riscv/corev.md > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-ad= dn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-ad= drn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-ad= dun.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-ad= durn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-cl= ip.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-cl= ipu.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-su= bn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-su= brn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-su= bun.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-su= burn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= c.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= chhsn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= chhsrn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= chhun.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= chhurn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= csn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= csrn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= cun.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ma= curn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-ms= u.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lhhsn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lhhsrn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lhhun.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lhhurn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lsn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lsrn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lun.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mu= lurn.c > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogenera= tion.c > > -- > 2.34.1 >