From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id EF0E43858D28 for ; Thu, 8 Sep 2022 04:22:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EF0E43858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x630.google.com with SMTP id z17so7093808eje.0 for ; Wed, 07 Sep 2022 21:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=+vyri/+qHdUsRRX+YDEKjHOZlKeoAKn1/T1NnVltgIo=; b=Afy+9nuY6PTiiFrj5HqlCvPALXvSzZEuUrobrOvD1zZokdTsweTqCTIKK2NPhPZl+v 4X22S5dYa0S9zPr3YrMD5kFrKlcKMmNvbjFmmmu4aYs26Xv+udtZzFtoalJbI7sHU1u7 CplfH7nqqFcaGVwgoskmm/BORSg207EtVmTQFJdc3UOfxn0UFJVlOWiLl+S2J6sbeAXG sc93fHXh59lmt+M1UazHE5d6IKjGXjNMACDWB9TOi1NKFexZo22m8l8fQiWLuVB8ucl4 fHAiZttkYsK5AedgpI1xlFX19YumjoTgnjRXYv/O/uPOpO6fOAA4dCCX4w4zDRO9NOf3 59Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=+vyri/+qHdUsRRX+YDEKjHOZlKeoAKn1/T1NnVltgIo=; b=25OHMTAqIxCBYK5tFR9u98hbsj6Nt0PyjwpuKGJo1Yt5fiIFWtwEnX5srLDiQ56fVP xENrcnr4qqm+512vF/DBhywLeq7v1ibaGSnIHXD0hKhVNBAmwvDb5XDv46FNdUxnxr7y XUZewihTJUEnpVtmAM/WDBy8DLEMVCJ+7gq025h9bFjq+VicbvICPJodlQC1EVRBrIi8 HhceNnlfib1udGoG1RIkRRftaLI8S/bndwJoQUF/lZ0txWtBDrLsmj3xIY0wNz4VXlu6 2XFi8mzpuAl+V+1EJk1OZxSTI/DKU+7EJvfmWaim2FdH2P4ZLW+vnnRZS5e2LncymAEq 3URw== X-Gm-Message-State: ACgBeo2raSGEovO/mW1a6+xfVchqyRHTABsemdDUEZzPRjMGNKghfkft 6eqY957t3oLo5TIRuVpsx83gOvTPoX9t/wNwI0Y= X-Google-Smtp-Source: AA6agR5I70VJA7xarOIYGtrbUXpt3HfBS1i6gw0vS2Qv8lZJ2xRIMs/BUmjnqlaeKipU7Gyx8I2eRm3l8wbIIGEReIs= X-Received: by 2002:a17:907:2e0d:b0:741:a3ec:7f92 with SMTP id ig13-20020a1709072e0d00b00741a3ec7f92mr4587807ejc.309.1662610976310; Wed, 07 Sep 2022 21:22:56 -0700 (PDT) MIME-Version: 1.0 References: <20220908015049.2506-1-jiawei@iscas.ac.cn> In-Reply-To: <20220908015049.2506-1-jiawei@iscas.ac.cn> From: Kito Cheng Date: Thu, 8 Sep 2022 12:22:44 +0800 Message-ID: Subject: Re: [PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc. To: jiawei Cc: GCC Patches , wuwei2016@iscas.ac.cn, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Jiawei: Could you add check in config/configure.ac and gcc/config.in to make sure the binutils has support for that or not? You can reference the commit for -misa-spec to see how it work and how it add: https://github.com/gcc-mirror/gcc/commit/4b81528241ca682025d92558ff6aeec91dafdca8 Thanks :) On Thu, Sep 8, 2022 at 9:51 AM jiawei wrote: > > From: Jiawei > > Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option, > it will add csr-check in .option section and pass this to assembler. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_file_start): New .option. > * config/riscv/riscv.opt: New options. > * doc/invoke.texi: New definations. > > --- > gcc/config/riscv/riscv.cc | 5 +++++ > gcc/config/riscv/riscv.opt | 6 ++++++ > gcc/doc/invoke.texi | 6 ++++++ > 3 files changed, 17 insertions(+) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 675d92c0961..e98e6b1f561 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5135,6 +5135,11 @@ riscv_file_start (void) > if (! riscv_mrelax) > fprintf (asm_out_file, "\t.option norelax\n"); > > + /* If the user specifies "-mcsr-check" on the command line then enable csr > + check in the assembler. */ > + if (riscv_mcsr_check) > + fprintf (asm_out_file, "\t.option csr-check\n"); > + > if (riscv_emit_attribute_p) > riscv_emit_attribute (); > } > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index fbca91b956c..3a12dd47310 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1) > Take advantage of linker relaxations to reduce the number of instructions > required to materialize symbol addresses. > > +mcsr-check > +Target Bool Var(riscv_mcsr_check) Init(1) > +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. > +The ISA-dependent CSR are only valid when the specific ISA is set. The > +read-only CSR can not be written by the CSR instructions. > + > Mask(64BIT) > > Mask(MUL) > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index dd3302fcd15..7caade26b94 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options. > -mbig-endian -mlittle-endian @gol > -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol > -mstack-protector-guard-offset=@var{offset}} > +-mcsr-check -mno-csr-check @gol > > @emph{RL78 Options} > @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol > @@ -28551,6 +28552,11 @@ linker relaxations. > Emit (do not emit) RISC-V attribute to record extra information into ELF > objects. This feature requires at least binutils 2.32. > > +@item -mcsr-check > +@itemx -mno-csr-check > +@opindex mcsr-check > +Enables or disables the CSR checking. > + > @item -malign-data=@var{type} > @opindex malign-data > Control how GCC aligns variables and constants of array, structure, or union > -- > 2.34.1 >