From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa32.google.com (mail-vk1-xa32.google.com [IPv6:2607:f8b0:4864:20::a32]) by sourceware.org (Postfix) with ESMTPS id 05FCD385840F for ; Fri, 28 Apr 2023 07:18:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 05FCD385840F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa32.google.com with SMTP id 71dfb90a1353d-440364c90d6so3189676e0c.0 for ; Fri, 28 Apr 2023 00:18:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682666283; x=1685258283; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=3r0+mOZDXi6Gnlzdk7SxGvvPE28tSokNoyfaxLqGNY0=; b=n+X7wUrxkAU72WyrtXOjsQ4KasfCMxWvUey2h37AmIBmM9kYp6oQylko1r0RkrPPjh 11HfGW+fXxNlcmZHq8OkZNooRwEEEg4K+ujamR3sw+Jb+2yN+V8cElICxQQKd9AbRAjK lM2NRkOXarIOwdwsxVI7QbMR+zsKaM9wrrLnjBAfisgUvj1lRXkk5437JNmayuOveLiO 4DrYNKOi4DBgxD+/XPjwTPO3KAbvpX0w1J1anz3pGw9RAkruRmE8vKabFAYSdoxL7ohu nC272P6aWctAonzrSB9tUuZb2QCVELgwuDXQLhdl5lQ77btifOsy4l06744u0iiKTNkH IVUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682666283; x=1685258283; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3r0+mOZDXi6Gnlzdk7SxGvvPE28tSokNoyfaxLqGNY0=; b=MAAD+SXGAo/KTnyg8UtKMVW5c5a6RjCxusDuYQ5GNa1UkZ5VOWBL8u46FcfOQD037h +ZoYfCUEPofRA1m0vhsJp0x7hvR2yQhl+rN6y520MmIIzn+2u7Tp5CjCmJL9mhRHzDeY uumQJgn/4B7jjhjeQ8orVDxdN8NrrTx5mDz28qVZ3Rego8ZPDbbqGFhOgtg0a8v52doR PDq9OCEoPIW7GccTFjmUzWSy3uC92kwWmaJclDiGnpIvHGh21C8ZTvIgURPy8rxepZPc wfoipEiqtbQ7vwg8O29kP2W8PoKUE1wGr3CMMvPMVZ0cOSr4a0OleQ3QlAmGmafBdf/w OmpQ== X-Gm-Message-State: AC+VfDz9cH+SjZayBJL501wDk30MTyCJ43rjXtcoYtH+nYgoMS+j9d6k NV3OHOxyGAW890A8hGFIkM5jtd13yITsXdiIlZ8= X-Google-Smtp-Source: ACHHUZ7QeUnNkWUmcRN2JhqAevQQcRk3yua04WjyAdfugqN6IYKE4JfV58KLCkGZAjL23OmSRZx6TOXUuUSpGB6S3Kw= X-Received: by 2002:a1f:4803:0:b0:440:3ef7:35ba with SMTP id v3-20020a1f4803000000b004403ef735bamr1635955vka.13.1682666283013; Fri, 28 Apr 2023 00:18:03 -0700 (PDT) MIME-Version: 1.0 References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> <20230428061210.2988035-3-christoph.muellner@vrull.eu> In-Reply-To: <20230428061210.2988035-3-christoph.muellner@vrull.eu> From: Kito Cheng Date: Fri, 28 Apr 2023 15:17:52 +0800 Message-ID: Subject: Re: [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: ok On Fri, Apr 28, 2023 at 2:15=E2=80=AFPM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > The current implementation triggers an assertion in > dwarf2out_frame_debug_cfa_offset() under certain circumstances. > The standard code uses REG_FRAME_RELATED_EXPR notes instead > of REG_CFA_OFFSET notes when saving registers on the stack. > So let's do this as well. > > gcc/ChangeLog: > > * config/riscv/thead.cc (th_mempair_save_regs): > Emit REG_FRAME_RELATED_EXPR notes in prologue. > > Signed-off-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/thead.cc | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc > index 75203805310..d7e3cf80d9b 100644 > --- a/gcc/config/riscv/thead.cc > +++ b/gcc/config/riscv/thead.cc > @@ -368,8 +368,12 @@ th_mempair_save_regs (rtx operands[4]) > rtx set2 =3D gen_rtx_SET (operands[2], operands[3]); > rtx insn =3D emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1= , set2))); > RTX_FRAME_RELATED_P (insn) =3D 1; > - add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set1)); > - add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set2)); > + > + REG_NOTES (insn) =3D alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, > + copy_rtx (set1), REG_NOTES (insn)); > + > + REG_NOTES (insn) =3D alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, > + copy_rtx (set2), REG_NOTES (insn)); > } > > /* Similar like riscv_restore_reg, but restores two registers from memor= y > -- > 2.40.1 >