From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 27325393BA60 for ; Wed, 26 Oct 2022 08:34:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 27325393BA60 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62f.google.com with SMTP id ud5so15753202ejc.4 for ; Wed, 26 Oct 2022 01:34:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=7Jw3HOURq78TLgg4xHHDtMfAFaXhP7S2tsQXMJSanKg=; b=N80ODQtetaS92dXqdDd/JfH7RxZDhFTPPNK5RxP8SydQLigL0BH4z4NCkMu5yk2KFg 6YyoMhxtjY0JvxXrkQpa2wvQfeGeKmCqY1R7DGJ4RPS3XmyWzViQoNwKY3KhZ8Da38yI 72LPHIEK/Yi/LKmlt8xSlrbwU7YSEqLkukgxQ6oIjmqm92nfWazH9pMtWzrJLnPs7nIB fX/wt9vpVayma4qs7fjD3bRTJX3rM4nw4z45FkTa/mI65XFef/RKN1Nz9VyYwFUJtfVK LKxxgmuLMbDN/PruNcLdzcTpQme+B4xOXjeNsjRjLzkM1cck885oJAZMURKy8xovi8v5 Ho0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7Jw3HOURq78TLgg4xHHDtMfAFaXhP7S2tsQXMJSanKg=; b=RtLcY/AeTAx7fIY20WpEYZo1nLJgLdg/XzyPpceTsSG7jbLNXGfBsPO++Use9xMX6Z mtYfDqlykk9chwoWTFUE9osHUXE6aDdiV052UV1bGrugSGzc3XTDbyComTl/Aj9QLcpH 0uxtZILQlzxBSYPba5B6kQjxkVw2DNFybcPxcSx8YoETwUOwjFtQ6FxEM4rgTUoqD+ga WsrUU8pgDrUR/h9/JoEJBcafnupwAu8W8YquRQvKu6FRBEX+jOevKWUk4PkqaAExiRjP Hu+petA9CkIeT6g20Aan08KvBCu5HDffla0NHKJQIrvNiTCd1p47pmeQpGhegxpyI8Hi ridg== X-Gm-Message-State: ACrzQf1yheIlqOZYhe194xrA3E5B8G67YNJUcwhhQqk8Rrs1zE1FEE28 jWXjbUESs7GonC32h5E0OpFdpG+4NNXC/Zv8ARDrNxiXht8= X-Google-Smtp-Source: AMsMyM523NJ+f9LpyO496nJoNt4BV711KAmJARmTXiOCscQWUzzZKPU0DGCl8YCGHsGyGawrEUFMuBKH7tu6Jr5OJ/8= X-Received: by 2002:a17:907:1c98:b0:78d:3b06:dc8f with SMTP id nb24-20020a1709071c9800b0078d3b06dc8fmr35580071ejc.58.1666773268579; Wed, 26 Oct 2022 01:34:28 -0700 (PDT) MIME-Version: 1.0 References: <20221024142414.161380-1-juzhe.zhong@rivai.ai> In-Reply-To: <20221024142414.161380-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Wed, 26 Oct 2022 16:34:16 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix typo. To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed with title tweak , thanks On Mon, Oct 24, 2022 at 10:24 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo. > > --- > gcc/config/riscv/riscv-modes.def | 46 ++++++++++++++++---------------- > 1 file changed, 23 insertions(+), 23 deletions(-) > > diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def > index 95f69e87e23..ea88442e117 100644 > --- a/gcc/config/riscv/riscv-modes.def > +++ b/gcc/config/riscv/riscv-modes.def > @@ -71,29 +71,29 @@ ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); > > /* > | Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | > - | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | > - | VNx1QI | MF4 | 32 | MF8 | 64 | > - | VNx2QI | MF2 | 16 | MF4 | 32 | > - | VNx4QI | M1 | 8 | MF2 | 16 | > - | VNx8QI | M2 | 4 | M1 | 8 | > - | VNx16QI | M4 | 2 | M2 | 4 | > - | VNx32QI | M8 | 1 | M4 | 2 | > - | VNx64QI | N/A | N/A | M8 | 1 | > - | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 | > - | VNx2(HI|HF) | M1 | 16 | MF2 | 32 | > - | VNx4(HI|HF) | M2 | 8 | M1 | 16 | > - | VNx8(HI|HF) | M4 | 4 | M2 | 8 | > - | VNx16(HI|HF)| M8 | 2 | M4 | 4 | > - | VNx32(HI|HF)| N/A | N/A | M8 | 2 | > - | VNx1(SI|SF) | M1 | 32 | MF2 | 64 | > - | VNx2(SI|SF) | M2 | 16 | M1 | 32 | > - | VNx4(SI|SF) | M4 | 8 | M2 | 16 | > - | VNx8(SI|SF) | M8 | 4 | M4 | 8 | > - | VNx16(SI|SF)| N/A | N/A | M8 | 4 | > - | VNx1(DI|DF) | N/A | N/A | M1 | 64 | > - | VNx2(DI|DF) | N/A | N/A | M2 | 32 | > - | VNx4(DI|DF) | N/A | N/A | M4 | 16 | > - | VNx8(DI|DF) | N/A | N/A | M8 | 8 | > + | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | > + | VNx1QI | MF4 | 32 | MF8 | 64 | > + | VNx2QI | MF2 | 16 | MF4 | 32 | > + | VNx4QI | M1 | 8 | MF2 | 16 | > + | VNx8QI | M2 | 4 | M1 | 8 | > + | VNx16QI | M4 | 2 | M2 | 4 | > + | VNx32QI | M8 | 1 | M4 | 2 | > + | VNx64QI | N/A | N/A | M8 | 1 | > + | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 | > + | VNx2(HI|HF) | M1 | 16 | MF2 | 32 | > + | VNx4(HI|HF) | M2 | 8 | M1 | 16 | > + | VNx8(HI|HF) | M4 | 4 | M2 | 8 | > + | VNx16(HI|HF)| M8 | 2 | M4 | 4 | > + | VNx32(HI|HF)| N/A | N/A | M8 | 2 | > + | VNx1(SI|SF) | M1 | 32 | MF2 | 64 | > + | VNx2(SI|SF) | M2 | 16 | M1 | 32 | > + | VNx4(SI|SF) | M4 | 8 | M2 | 16 | > + | VNx8(SI|SF) | M8 | 4 | M4 | 8 | > + | VNx16(SI|SF)| N/A | N/A | M8 | 4 | > + | VNx1(DI|DF) | N/A | N/A | M1 | 64 | > + | VNx2(DI|DF) | N/A | N/A | M2 | 32 | > + | VNx4(DI|DF) | N/A | N/A | M4 | 16 | > + | VNx8(DI|DF) | N/A | N/A | M8 | 8 | > */ > > /* Define RVV modes whose sizes are multiples of 64-bit chunks. */ > -- > 2.36.1 >