From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id 665ED3858C50 for ; Mon, 24 Oct 2022 10:19:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 665ED3858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x532.google.com with SMTP id z97so29305144ede.8 for ; Mon, 24 Oct 2022 03:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=LAb1axeHPiocaxJEeP56idqf0RJU8omaqalUDNw3PTE=; b=mxi/DI8/xl/K7TYoLdqVW4O4afomceo+UMdzhGzX23N9tK0VsAQQd4CdGQCOZRvG9t aO01sVnWbxP6WkNDV00ZhI5OfaQpiNVX+ZpKwJgQ+gq4c/J2IfqbZIkANOYpbO6Z41gH 8e1cwG6OELIGD+i68XOfuyRc4HveE1dbBEPrhGI2yr6HEnrLzDvgOg9TYspJB57m8wZv 5K9t/We1/XiUCBuCd2+xNMPpUYQ8RIl2Tu9x2S8SrKfQOraqCYS+WfrObVn9jeNMoQY5 tmhlxk1sE6zfTwT3Atjkd1JpfT82f3A3Yty54XD2uwZPKAQ8n/8IP6l9ks9DponmPxft Qb3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LAb1axeHPiocaxJEeP56idqf0RJU8omaqalUDNw3PTE=; b=1Oe/1wcJsnGkkdiLkzv1MAEf1SH3W5+MHcKJk3qOQ5KVuy3Ig413u4/JJ3o5eaf7/4 GsMqLvSieSryMt4XZekq3jTdIXKMywdZ6pc1mUYV7fsnS7FqP60GsypkzW3LtbvrX+FP gUQTLsWBGkS1GGYj5Oh8oT/iqyaGdffsLkuqD1/c/i5hqkuvn9NLwJW7zxznW10gGSsE ME9c62nFgWfGdLBQpdF2qKSBGEp323IbHBcQaCl3rXZmIXV+0rzHo9XRyqBhz6I2baRF ovAgfvavWNgPkeQWP3iM8EkFTQ3C+uAY8EuITKqNYxj7pa1ujectxJqO/T8XNHwP1ZDb PrdQ== X-Gm-Message-State: ACrzQf2H9zZvAeWgbcnB78nreu7hCjZJjbgp5rhbtVkdCUpTFTzQYttx yj7kdca2/5npaucCTzJWeQnf1wIO9cxzoSO9Oos= X-Google-Smtp-Source: AMsMyM7fp0CphhAo0WO2Sh4hssIIz1ZkYUtzJ5aYkR/CNyYL19m5twLq+R4wN7lYmjixRLCUW3m7M8mpwxG4gTf52/U= X-Received: by 2002:aa7:df08:0:b0:461:d9a2:b247 with SMTP id c8-20020aa7df08000000b00461d9a2b247mr2423897edy.54.1666606738965; Mon, 24 Oct 2022 03:18:58 -0700 (PDT) MIME-Version: 1.0 References: <20220930020523.21483-1-kito.cheng@sifive.com> In-Reply-To: <20220930020523.21483-1-kito.cheng@sifive.com> From: Kito Cheng Date: Mon, 24 Oct 2022 18:18:47 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Support --target-help for -mcpu/-mtune To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, jim.wilson.gcc@gmail.com, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed. On Fri, Sep 30, 2022 at 10:06 AM Kito Cheng wrote: > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_tunes): New. > (riscv_get_valid_option_values): New. > (TARGET_GET_VALID_OPTION_VALUES): New. > * config/riscv/riscv-cores.def (RISCV_TUNE): New, define options > for tune here. > (RISCV_CORE): Fix comment. > * config/riscv/riscv.cc (riscv_tune_info_table): Move definition to > riscv-cores.def. > --- > gcc/common/config/riscv/riscv-common.cc | 46 +++++++++++++++++++++++++ > gcc/config/riscv/riscv-cores.def | 35 ++++++++++++++++--- > gcc/config/riscv/riscv.cc | 9 ++--- > 3 files changed, 80 insertions(+), 10 deletions(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index c39ed2e2696..697bfe435c8 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -224,6 +224,14 @@ static const riscv_cpu_info riscv_cpu_tables[] = > {NULL, NULL, NULL} > }; > > +static const char *riscv_tunes[] = > +{ > +#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \ > + TUNE_NAME, > +#include "../../../config/riscv/riscv-cores.def" > + NULL > +}; > + > static const char *riscv_supported_std_ext (void); > > static riscv_subset_list *current_subset_list = NULL; > @@ -1683,6 +1691,41 @@ riscv_compute_multilib ( > return xstrdup (multilib_infos[best_match_multi_lib].path.c_str ()); > } > > +vec > +riscv_get_valid_option_values (int option_code, > + const char *prefix ATTRIBUTE_UNUSED) > +{ > + vec v; > + v.create (0); > + opt_code opt = (opt_code) option_code; > + > + switch (opt) > + { > + case OPT_mtune_: > + { > + const char **tune = &riscv_tunes[0]; > + for (;*tune; ++tune) > + v.safe_push (*tune); > + > + const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0]; > + for (;cpu_info->name; ++cpu_info) > + v.safe_push (cpu_info->name); > + } > + break; > + case OPT_mcpu_: > + { > + const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0]; > + for (;cpu_info->name; ++cpu_info) > + v.safe_push (cpu_info->name); > + } > + break; > + default: > + break; > + } > + > + return v; > +} > + > #undef TARGET_COMPUTE_MULTILIB > #define TARGET_COMPUTE_MULTILIB riscv_compute_multilib > #endif > @@ -1701,4 +1744,7 @@ static const struct default_options riscv_option_optimization_table[] = > #undef TARGET_HANDLE_OPTION > #define TARGET_HANDLE_OPTION riscv_handle_option > > +#undef TARGET_GET_VALID_OPTION_VALUES > +#define TARGET_GET_VALID_OPTION_VALUES riscv_get_valid_option_values > + > struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def > index ecb5e213d98..b84ad999ac1 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -17,19 +17,46 @@ > along with GCC; see the file COPYING3. If not see > . */ > > +/* This is a list of tune that implement RISC-V. > + > + Before using #include to read this file, define a macro: > + > + RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) > + > + The TUNE_NAME is the name of the micro-arch, represented as a string. > + The PIPELINE_MODEL is the pipeline model of the micro-arch, represented as a > + string, defined in riscv.md. > + The TUNE_INFO is the detail cost model for this core, represented as an > + identifier, reference to riscv.cc. */ > + > +#ifndef RISCV_TUNE > +#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) > +#endif > + > +RISCV_TUNE("rocket", generic, rocket_tune_info) > +RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) > +RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) > +RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info) > +RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) > +RISCV_TUNE("size", generic, optimize_size_tune_info) > + > +#undef RISCV_TUNE > + > /* This is a list of cores that implement RISC-V. > > Before using #include to read this file, define a macro: > > - RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO) > + RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH) > > The CORE_NAME is the name of the core, represented as a string. > The ARCH is the default arch of the core, represented as a string, > can be NULL if no default arch. > The MICRO_ARCH is the name of the core for which scheduling decisions > - will be made, represented as an identifier. > - The TUNE_INFO is the detail cost model for this core, represented as an > - identifier, reference to riscv-tunes.def. */ > + will be made, represented as an identifier. */ > + > +#ifndef RISCV_CORE > +#define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH) > +#endif > > RISCV_CORE("sifive-e20", "rv32imc", "rocket") > RISCV_CORE("sifive-e21", "rv32imac", "rocket") > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 0d618315828..00b7df02e2e 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -395,12 +395,9 @@ static const unsigned gpr_save_reg_order[] = { > > /* A table describing all the processors GCC knows about. */ > static const struct riscv_tune_info riscv_tune_info_table[] = { > - { "rocket", generic, &rocket_tune_info }, > - { "sifive-3-series", generic, &rocket_tune_info }, > - { "sifive-5-series", generic, &rocket_tune_info }, > - { "sifive-7-series", sifive_7, &sifive_7_tune_info }, > - { "thead-c906", generic, &thead_c906_tune_info }, > - { "size", generic, &optimize_size_tune_info }, > +#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \ > + { TUNE_NAME, PIPELINE_MODEL, & TUNE_INFO}, > +#include "riscv-cores.def" > }; > > void riscv_frame_info::reset(void) > -- > 2.37.2 >