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From: Kito Cheng <kito.cheng@gmail.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com,
	jeffreyalaw@gmail.com,  rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Support in-order floating-point reduction
Date: Thu, 20 Jul 2023 15:42:56 +0800	[thread overview]
Message-ID: <CA+yXCZCPUVOFnqe9e=954YshAyO=R1_rhGjuJxKYWndDSdu9MQ@mail.gmail.com> (raw)
In-Reply-To: <20230720073406.239379-1-juzhe.zhong@rivai.ai>

Seems like there is a potential vsetvli optimization chance in the example?

> After this patch:
> foo:
>         lui     a5,%hi(.LC0)
>         flw     fa0,%lo(.LC0)(a5)
>         ble     a1,zero,.L4
> .L3:
>         vsetvli a5,a1,e32,m1,ta,ma
>         vle32.v v1,0(a0)
>         slli    a4,a5,2
>         vsetivli        zero,1,e32,m1,ta,ma

This could just use "vsetvli a5,a1,e32,m1,ta,ma"

>         sub     a1,a1,a5
>         vfmv.s.f        v2,fa0
>         add     a0,a0,a4
>         vsetvli zero,a5,e32,m1,ta,ma

And then this can be removed too.

>         vfredosum.vs    v1,v1,v2
>         vfmv.f.s        fa0,v1
>         bne     a1,zero,.L3
>         ret
> .L4:
>         ret

  parent reply	other threads:[~2023-07-20  7:43 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-20  7:34 Juzhe-Zhong
2023-07-20  7:41 ` Robin Dapp
2023-07-20  7:42   ` juzhe.zhong
2023-07-20  7:57     ` Robin Dapp
2023-07-20  7:59       ` juzhe.zhong
2023-07-20  8:03         ` Kito Cheng
2023-07-20  8:16           ` juzhe.zhong
2023-07-20  8:24             ` Kito Cheng
2023-07-20  8:53               ` juzhe.zhong
2023-07-20  7:42 ` Kito Cheng [this message]
2023-07-20  7:53   ` juzhe.zhong

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