From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa31.google.com (mail-vk1-xa31.google.com [IPv6:2607:f8b0:4864:20::a31]) by sourceware.org (Postfix) with ESMTPS id 839EC3858C2F for ; Thu, 27 Jul 2023 11:57:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 839EC3858C2F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa31.google.com with SMTP id 71dfb90a1353d-4865c9f9d9bso842114e0c.1 for ; Thu, 27 Jul 2023 04:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690459048; x=1691063848; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=muq8/kewNhUTnRTSlAPF9vNWrvdo4egk1NoCFMKVhgs=; b=rphCdTRb8AjBfQEgO37/bUrO1nfBMa0tNJPTzWLgqe+RRgShTFhamPMc/peJtP/J7/ gb6eTKPCwP5/xxzbIVZaqAjc4CHe0B6OpH9CFrvUsh6mNsL7fmIKRblY6Glm9WniNsv0 tEMpk86QIP8ewZXM8UUISBWlVUGK4hFHqv0LQ79Tg1+UEq8HQI34efV23hK7aWYKP4G6 ORh9vVt3pGxJF58tCjtyvqL2HrEok56vRzvX85exG4dVZcyZwIM3F9Pyw48RM5ikTyZQ AKBkE8uqGra6tVeP4O7g38vlhin0a/QYGPBv46H2C4kgaLfNcoUvo6Lf9afJUFub34gH PZAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690459048; x=1691063848; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=muq8/kewNhUTnRTSlAPF9vNWrvdo4egk1NoCFMKVhgs=; b=MChY/4NJG45j9Tdj4NzQO5yyDL2EQTjWd2pEqunw8rOz/98uxNcVue2/OVKKeDy6Hc V1aVGBhH5QsS/KvZ7KNTCO2+x3J4vJ7x1BRGq0VYmaWVy1PcHfHfe89w/UgOLTYrn+mr /JffhaJE8wnAXszta59fJqHvuUJ8MXKTTTOWtghi2Q3vQ/ADh3wHVsBUMBtUEpBic80J WMIxYLvuB9kxe6HJ35OmVVpXq4VZUCp1QwLVWk3FC2cKK78CfYqk1/uCjx7jItIFNpIE nQB9KbUry+5F2QFcu0xver+jLZwJ3id5ccjd2sw04LQAQCG7hvZh2joZRTnjjVQJo4Uh v7cQ== X-Gm-Message-State: ABy/qLYV5k9dZaBUqMbJRIEa37zGrAT5CD7qTSOHkBILEndWZCA4g+t3 6IxGufj4AhdCIMT/5uItf0liThhBmleG8P5rnG8= X-Google-Smtp-Source: APBJJlGp7ne4KRsNgwFh2X09cqmt6SNHMOP/0Ggr1/433nRe4f2SjSwk3AOrRH4RJC5MRkS6xri98/B6S1oM01laSl8= X-Received: by 2002:a05:6122:2491:b0:47d:57a0:b8ba with SMTP id by17-20020a056122249100b0047d57a0b8bamr443517vkb.6.1690459047663; Thu, 27 Jul 2023 04:57:27 -0700 (PDT) MIME-Version: 1.0 References: <20230727094859.3884298-1-demin.han@starfivetech.com> <4F1CE7168EFB3E1A+2023072718223714228879@rivai.ai> In-Reply-To: <4F1CE7168EFB3E1A+2023072718223714228879@rivai.ai> From: Kito Cheng Date: Thu, 27 Jul 2023 19:57:16 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative To: "juzhe.zhong@rivai.ai" Cc: "demin.han" , gcc-patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: My first impression is those emit_insn (gen_rtx_SET()) seems necessary, but I got the point after I checked vector.md :P Committed to trunk, thanks :) On Thu, Jul 27, 2023 at 6:23=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > Oh, YES. > > Thanks for fixing it. It makes sense since the ternary operations in "vec= tor.md" > generate "vmv.v.v" according to RA. > > Thanks for fixing it. > > @kito: Could you confirm it? If it's ok to you, commit it for Han (I am l= azy to commit patches :). > > > > juzhe.zhong@rivai.ai > > From: demin.han > Date: 2023-07-27 17:48 > To: gcc-patches@gcc.gnu.org > CC: kito.cheng@gmail.com; juzhe.zhong@rivai.ai > Subject: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alt= ernative > When pass split2 starts, which_alternative is random depending on > last set of certain pass. > > Even initialized, the generated movement is redundant. > The movement can be generated by assembly output template. > > Signed-off-by: demin.han > > gcc/ChangeLog: > > * config/riscv/autovec.md: Delete which_alternative use in split > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test. > > --- > gcc/config/riscv/autovec.md | 12 ------------ > .../gcc.target/riscv/rvv/autovec/madd-split2-1.c | 13 +++++++++++++ > 2 files changed, 13 insertions(+), 12 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2= -1.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index d899922586a..b7ea3101f5a 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma" > [(const_int 0)] > { > riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > - if (which_alternative =3D=3D 2) > - emit_insn (gen_rtx_SET (operands[0], operands[3])); > rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), > riscv_vector::RVV_TERNOP, ops, operands[4]); > @@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma" > [(const_int 0)] > { > riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > - if (which_alternative =3D=3D 2) > - emit_insn (gen_rtx_SET (operands[0], operands[3])); > rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), > riscv_vector::RVV_TERNOP, ops, operands[4]); > @@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma" > [(const_int 0)] > { > riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > - if (which_alternative =3D=3D 2) > - emit_insn (gen_rtx_SET (operands[0], operands[3])); > rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, <= VF:MODE>mode), > riscv_vector::RVV_TERNOP, ops, operands[4]); > @@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma" > [(const_int 0)] > { > riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > - if (which_alternative =3D=3D 2) > - emit_insn (gen_rtx_SET (operands[0], operands[3])); > rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLU= S, mode), > riscv_vector::RVV_TERNOP, ops, operands[4]); > @@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms" > [(const_int 0)] > { > riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > - if (which_alternative =3D=3D 2) > - emit_insn (gen_rtx_SET (operands[0], operands[3])); > rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, = mode), > riscv_vector::RVV_TERNOP, ops, operands[4]); > @@ -1242,8 +1232,6 @@ (define_insn_and_split "*fnms" > [(const_int 0)] > { > riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); > - if (which_alternative =3D=3D 2) > - emit_insn (gen_rtx_SET (operands[0], operands[3])); > rtx ops[] =3D {operands[0], operands[1], operands[2], operands[3], o= perands[0]}; > riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MIN= US, mode), > riscv_vector::RVV_TERNOP, ops, operands[4]); > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > new file mode 100644 > index 00000000000..14a9802667e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > @@ -0,0 +1,13 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvl256b -O3 -fno-cprop-registers -fno-= dce --param riscv-autovec-preference=3Dscalable" } */ > + > +long > +foo (long *__restrict a, long *__restrict b, long n) > +{ > + long i; > + for (i =3D 0; i < n; ++i) > + a[i] =3D b[i] + i * 8; > + return a[1]; > +} > + > +/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */ > -- > 2.41.0 > >