From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x929.google.com (mail-ua1-x929.google.com [IPv6:2607:f8b0:4864:20::929]) by sourceware.org (Postfix) with ESMTPS id 8408238555A2 for ; Tue, 7 Mar 2023 13:46:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8408238555A2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x929.google.com with SMTP id d12so8847230uak.10 for ; Tue, 07 Mar 2023 05:46:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678196769; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Z4pZVRy0Of68IBlVx3GKHCObUzAPs2KGDzLQayLZ5VI=; b=hdl6WRHwTUnBcf/lI8J+yonvWttu0nUcSNETf6NIOeL0pe07tfaBb0Ql4p7NsZcpmN 9zsI6ixh6H49Yn8ivVFippQRIp3n6hRYabpJJ3s/9Ocup9PTzYICDdzm0QD2PKCsEfn/ B5rIcsMn/ivu22M+LSXBgqgHdg7Oo+R361uuJmOk4USWlFd7EYxFfEw3QXhFdSy7Nu/S dtNRrfeXNW6Ir4l5PaFiLweH7RA6PsmuiTfCPPPfqHhSUkUgm4R24kJ+yP12ee+SQIS0 7lQcn5b3K+7WayTJV6Tj9HcyinomWFGeB4G4xbDzITJJ9DesJJC+iEfJx4nOp1Jed4u+ iLnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678196769; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z4pZVRy0Of68IBlVx3GKHCObUzAPs2KGDzLQayLZ5VI=; b=J9Z6xd24A4o4OlwGbpZji7C1s3nfoWndBVnhtPhVGH7CMUMVdXJPnJ6vlSBOwBx+dX /EFxk845mqBKWlg0SLt5H+N1cUX1mAY8DZ2G30nQ0XSpJJne0ADWm9eSF7cG4dbXbUa8 L4D9hjxjdolcWMJtfDXVC2Sw5JGNdW1hONScUHBSgwiY5U3zB/1fgQEAWfq3/3/bLujT hLwACOF49SazEKON0d4yfV1IsJQxLQKN0t7RQjWdLRNrrWzsqsjGd01c30u+dloLgbzF fHDX1aVifJwX+ppzoBZdPH52If9MqSnkJJa8EvIvet0gFnpZPAblcNIg72OdaE4XX8C8 4gsw== X-Gm-Message-State: AO0yUKUW9GXcD9wfKYzcUr6MlgJq7Gthp0eRGlRUgwPR71OxgcjZkHBK qeeLM2CopNYLdKZN6gcT1rT0F8j6Y6zRzBzYUY8= X-Google-Smtp-Source: AK7set8Ia89AWIHbqQo2fL/BvYS0tbbdt3j7FcQ2rp3/fKkl0tVEo7tSl7qyvYRMYljlWfKvGvV7XSifZIsTg3X+rn8= X-Received: by 2002:ab0:4a05:0:b0:68b:6325:4061 with SMTP id q5-20020ab04a05000000b0068b63254061mr10091158uae.0.1678196767450; Tue, 07 Mar 2023 05:46:07 -0800 (PST) MIME-Version: 1.0 References: <20230303023141.125126-1-pan2.li@intel.com> <20230307120515.258058-1-pan2.li@intel.com> In-Reply-To: <20230307120515.258058-1-pan2.li@intel.com> From: Kito Cheng Date: Tue, 7 Mar 2023 21:45:55 +0800 Message-ID: Subject: Re: [PATCH v5] RISC-V: Bugfix for rvv bool mode precision adjustment To: "Li, Pan2" Cc: GCC Patches , =?UTF-8?B?6ZKf5bGF5ZOy?= , Kito Cheng , Richard Biener , "richard.sandiford" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_35_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Pan: Really appreciate your patch for fixing this issue! committed to trunk with minor commit log tweak :) On Tue, Mar 7, 2023 at 8:05=E2=80=AFPM pan2.li--- via Gcc-patches wrote: > > From: Pan Li > > Fix the bug of the rvv bool mode precision with the adjustment. > The bits size of vbool*_t will be adjusted to > [1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The > adjusted mode precison of vbool*_t will help underlying pass to > make the right decision for both the correctness and optimization= . > > Given below sample code: > void test_1(int8_t * restrict in, int8_t * restrict out) > { > vbool8_t v2 =3D *(vbool8_t*)in; > vbool16_t v5 =3D *(vbool16_t*)in; > *(vbool16_t*)(out + 200) =3D v5; > *(vbool8_t*)(out + 100) =3D v2; > } > > Before the precision adjustment: > addi a4,a1,100 > vsetvli a5,zero,e8,m1,ta,ma > addi a1,a1,200 > vlm.v v24,0(a0) > vsm.v v24,0(a4) > // Need one vsetvli and vlm.v for correctness here. > vsm.v v24,0(a1) > > After the precision adjustment: > csrr t0,vlenb > slli t1,t0,1 > csrr a3,vlenb > sub sp,sp,t1 > slli a4,a3,1 > add a4,a4,sp > sub a3,a4,a3 > vsetvli a5,zero,e8,m1,ta,ma > addi a2,a1,200 > vlm.v v24,0(a0) > vsm.v v24,0(a3) > addi a1,a1,100 > vsetvli a4,zero,e8,mf2,ta,ma > csrr t0,vlenb > vlm.v v25,0(a3) > vsm.v v25,0(a2) > slli t1,t0,1 > vsetvli a5,zero,e8,m1,ta,ma > vsm.v v24,0(a1) > add sp,sp,t1 > jr ra > > However, there may be some optimization opportunates after > the mode precision adjustment. It can be token care of in > the RISC-V backend in the underlying separted PR(s). > > PR 108185 > PR 108654 > > gcc/ChangeLog: > > * config/riscv/riscv-modes.def (ADJUST_PRECISION): > * config/riscv/riscv.cc (riscv_v_adjust_precision): > * config/riscv/riscv.h (riscv_v_adjust_precision): > * genmodes.cc (ADJUST_PRECISION): > (emit_mode_adjustments): > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/pr108185-1.c: New test. > * gcc.target/riscv/pr108185-2.c: New test. > * gcc.target/riscv/pr108185-3.c: New test. > * gcc.target/riscv/pr108185-4.c: New test. > * gcc.target/riscv/pr108185-5.c: New test. > * gcc.target/riscv/pr108185-6.c: New test. > * gcc.target/riscv/pr108185-7.c: New test. > * gcc.target/riscv/pr108185-8.c: New test. > > Signed-off-by: Pan Li > Co-authored-by: Ju-Zhe Zhong > --- > gcc/config/riscv/riscv-modes.def | 8 +++ > gcc/config/riscv/riscv.cc | 12 ++++ > gcc/config/riscv/riscv.h | 1 + > gcc/genmodes.cc | 28 +++++++- > gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77 +++++++++++++++++++++ > 12 files changed, 600 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-7.c > create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-8.c > > diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-mo= des.def > index d5305efa8a6..110bddce851 100644 > --- a/gcc/config/riscv/riscv-modes.def > +++ b/gcc/config/riscv/riscv-modes.def > @@ -72,6 +72,14 @@ ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_= bytes_per_vector_chunk); > ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_c= hunk); > ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); > > +ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); > +ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); > +ADJUST_PRECISION (VNx4BI, riscv_v_adjust_precision (VNx4BImode, 4)); > +ADJUST_PRECISION (VNx8BI, riscv_v_adjust_precision (VNx8BImode, 8)); > +ADJUST_PRECISION (VNx16BI, riscv_v_adjust_precision (VNx16BImode, 16)); > +ADJUST_PRECISION (VNx32BI, riscv_v_adjust_precision (VNx32BImode, 32)); > +ADJUST_PRECISION (VNx64BI, riscv_v_adjust_precision (VNx64BImode, 64)); > + > /* > | Mode | MIN_VLEN=3D32 | MIN_VLEN=3D32 | MIN_VLEN=3D64 | MIN_V= LEN=3D64 | > | | LMUL | SEW/LMUL | LMUL | SEW/LMUL = | > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index f11b7949a49..ac5c2527fde 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -1003,6 +1003,18 @@ riscv_v_adjust_nunits (machine_mode mode, int scal= e) > return scale; > } > > +/* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct > + PRECISION size for corresponding machine_mode. */ > + > +poly_int64 > +riscv_v_adjust_precision (machine_mode mode, int scale) > +{ > + if (riscv_v_ext_vector_mode_p (mode)) > + return riscv_vector_chunks * scale; > + > + return scale; > +} > + > /* Return true if X is a valid address for machine mode MODE. If it is, > fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in > effect. */ > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 5bc7f2f467d..15b9317a8ce 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -1025,6 +1025,7 @@ extern unsigned riscv_stack_boundary; > extern unsigned riscv_bytes_per_vector_chunk; > extern poly_uint16 riscv_vector_chunks; > extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); > +extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); > /* The number of bits and bytes in a RVV vector. */ > #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_= bytes_per_vector_chunk * 8)) > #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv= _bytes_per_vector_chunk)) > diff --git a/gcc/genmodes.cc b/gcc/genmodes.cc > index 2d418f09aab..715787b8f48 100644 > --- a/gcc/genmodes.cc > +++ b/gcc/genmodes.cc > @@ -114,6 +114,7 @@ static struct mode_adjust *adj_alignment; > static struct mode_adjust *adj_format; > static struct mode_adjust *adj_ibit; > static struct mode_adjust *adj_fbit; > +static struct mode_adjust *adj_precision; > > /* Mode class operations. */ > static enum mode_class > @@ -819,6 +820,7 @@ make_vector_mode (enum mode_class bclass, > #define ADJUST_NUNITS(M, X) _ADD_ADJUST (nunits, M, X, RANDOM, RANDOM= ) > #define ADJUST_BYTESIZE(M, X) _ADD_ADJUST (bytesize, M, X, RANDOM, RAND= OM) > #define ADJUST_ALIGNMENT(M, X) _ADD_ADJUST (alignment, M, X, RANDOM, RAN= DOM) > +#define ADJUST_PRECISION(M, X) _ADD_ADJUST (precision, M, X, RANDOM, RAN= DOM) > #define ADJUST_FLOAT_FORMAT(M, X) _ADD_ADJUST (format, M, X, FLOAT, F= LOAT) > #define ADJUST_IBIT(M, X) _ADD_ADJUST (ibit, M, X, ACCUM, UACCUM) > #define ADJUST_FBIT(M, X) _ADD_ADJUST (fbit, M, X, FRACT, UACCUM) > @@ -1794,6 +1796,7 @@ emit_real_format_for_mode (void) > static void > emit_mode_adjustments (void) > { > + int c; > struct mode_adjust *a; > struct mode_data *m; > > @@ -1829,8 +1832,9 @@ emit_mode_adjustments (void) > " (mode_precision[E_%smode], mode_nunits[E_%smode]);\n", > m->name, m->name); > printf (" mode_precision[E_%smode] =3D ps * old_factor;\n", m->= name); > - printf (" mode_size[E_%smode] =3D exact_div (mode_precision[E_%= smode]," > - " BITS_PER_UNIT);\n", m->name, m->name); > + printf (" if (!multiple_p (mode_precision[E_%smode]," > + " BITS_PER_UNIT, &mode_size[E_%smode]))\n", m->name, m->nam= e); > + printf (" mode_size[E_%smode] =3D -1;\n", m->name); > printf (" mode_nunits[E_%smode] =3D ps;\n", m->name); > printf (" adjust_mode_mask (E_%smode);\n", m->name); > printf (" }\n"); > @@ -1963,6 +1967,26 @@ emit_mode_adjustments (void) > printf ("\n /* %s:%d */\n REAL_MODE_FORMAT (E_%smode) =3D %s;\n", > a->file, a->line, a->mode->name, a->adjustment); > > + /* Adjust precision to the actual bits size. */ > + for (a =3D adj_precision; a; a =3D a->next) > + switch (a->mode->cl) > + { > + case MODE_VECTOR_BOOL: > + printf ("\n /* %s:%d. */\n ps =3D %s;\n", a->file, a->line, > + a->adjustment); > + printf (" mode_precision[E_%smode] =3D ps;\n", a->mode->name); > + break; > + default: > + internal_error ("invalid use of ADJUST_PRECISION for mode %s", > + a->mode->name); > + /* NOTREACHED. */ > + } > + > + /* Ensure there is no mode size equals -1. */ > + for_all_modes (c, m) > + printf ("\n gcc_assert (maybe_ne (mode_size[E_%smode], -1));\n", > + m->name); > + > puts ("}"); > } > > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-1.c b/gcc/testsuite/= gcc.target/riscv/pr108185-1.c > new file mode 100644 > index 00000000000..e70960c5b6d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-1.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool1_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool1_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool1_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool1_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool1_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 18 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-2.c b/gcc/testsuite/= gcc.target/riscv/pr108185-2.c > new file mode 100644 > index 00000000000..dcc7a644a88 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-2.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool2_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool2_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool2_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool2_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool2_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 17 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-3.c b/gcc/testsuite/= gcc.target/riscv/pr108185-3.c > new file mode 100644 > index 00000000000..3af0513e006 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-3.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool4_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool4_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool4_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool4_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool4_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 16 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-4.c b/gcc/testsuite/= gcc.target/riscv/pr108185-4.c > new file mode 100644 > index 00000000000..ea3c360d756 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-4.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool8_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool8_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool8_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool8_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 15 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-5.c b/gcc/testsuite/= gcc.target/riscv/pr108185-5.c > new file mode 100644 > index 00000000000..9fc659d2402 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-5.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool16_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool16_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool16_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool16_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool16_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 14 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-6.c b/gcc/testsuite/= gcc.target/riscv/pr108185-6.c > new file mode 100644 > index 00000000000..98275e5267d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-6.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool32_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool32_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool32_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool32_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool32_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 13 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-7.c b/gcc/testsuite/= gcc.target/riscv/pr108185-7.c > new file mode 100644 > index 00000000000..8f6f0b11f09 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-7.c > @@ -0,0 +1,68 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool64_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool64_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool64_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool64_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool64_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool64_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 6 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-8.c b/gcc/testsuite/= gcc.target/riscv/pr108185-8.c > new file mode 100644 > index 00000000000..d96959dd064 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr108185-8.c > @@ -0,0 +1,77 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ > + > +#include "riscv_vector.h" > + > +void > +test_vbool1_then_vbool1(int8_t * restrict in, int8_t * restrict out) { > + vbool1_t v1 =3D *(vbool1_t*)in; > + vbool1_t v2 =3D *(vbool1_t*)in; > + > + *(vbool1_t*)(out + 100) =3D v1; > + *(vbool1_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool2_then_vbool2(int8_t * restrict in, int8_t * restrict out) { > + vbool2_t v1 =3D *(vbool2_t*)in; > + vbool2_t v2 =3D *(vbool2_t*)in; > + > + *(vbool2_t*)(out + 100) =3D v1; > + *(vbool2_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool4_then_vbool4(int8_t * restrict in, int8_t * restrict out) { > + vbool4_t v1 =3D *(vbool4_t*)in; > + vbool4_t v2 =3D *(vbool4_t*)in; > + > + *(vbool4_t*)(out + 100) =3D v1; > + *(vbool4_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool8_then_vbool8(int8_t * restrict in, int8_t * restrict out) { > + vbool8_t v1 =3D *(vbool8_t*)in; > + vbool8_t v2 =3D *(vbool8_t*)in; > + > + *(vbool8_t*)(out + 100) =3D v1; > + *(vbool8_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool16_then_vbool16(int8_t * restrict in, int8_t * restrict out) { > + vbool16_t v1 =3D *(vbool16_t*)in; > + vbool16_t v2 =3D *(vbool16_t*)in; > + > + *(vbool16_t*)(out + 100) =3D v1; > + *(vbool16_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool32_then_vbool32(int8_t * restrict in, int8_t * restrict out) { > + vbool32_t v1 =3D *(vbool32_t*)in; > + vbool32_t v2 =3D *(vbool32_t*)in; > + > + *(vbool32_t*)(out + 100) =3D v1; > + *(vbool32_t*)(out + 200) =3D v2; > +} > + > +void > +test_vbool64_then_vbool64(int8_t * restrict in, int8_t * restrict out) { > + vbool64_t v1 =3D *(vbool64_t*)in; > + vbool64_t v2 =3D *(vbool64_t*)in; > + > + *(vbool64_t*)(out + 100) =3D v1; > + *(vbool64_t*)(out + 200) =3D v2; > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*m1,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 7 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 14 } } */ > -- > 2.34.1 >