From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2f.google.com (mail-vs1-xe2f.google.com [IPv6:2607:f8b0:4864:20::e2f]) by sourceware.org (Postfix) with ESMTPS id 8CD413858C36 for ; Mon, 21 Nov 2022 03:11:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8CD413858C36 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2f.google.com with SMTP id i2so10017263vsc.1 for ; Sun, 20 Nov 2022 19:11:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=vakBaGwOy5auPWUGS6zxA0tHQ/WYJTEsk9r0j9vzHoc=; b=ZqGC4/lu9HAfRXfIrIv1pr+wZLI/XZDeVI06GnAIHvdRCtLEuu6Rmo6f33/5aFb1yb 2PnoVlT0NrRq0EcBZvJ7G8OBX9vrROMtILRUx7WVv9VH6PM5IhxFG4jVegXWSJLODzje laqIK2Yq4IHm/6oATQE+ArzOSk5fL7UlLe5DCl5d5iKMw+oX1krL0YiPQInjj+5DPiAo qVh4OjTzt5BDQdiiqz83X/rSxyABXw+88u+nqKbH3aBKP9YcH22roNKY+GYvjRmBsyrj 1y+ieQg5PtZOoKLTvLiIAdHcyvyVq+dLlMaGOugGsYkdsslB5xgbF92FzguhL+05mraN 2b6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vakBaGwOy5auPWUGS6zxA0tHQ/WYJTEsk9r0j9vzHoc=; b=gJN7WD2b3AFkOmqWgSnnVi82kgkpH8nSimBNK1a+jINh86yq9QkVnf+HBfhGJgZdKG WbRjCJPlCWsr8KbvaT9qGQms6UTyLQ+2AHPyRhjCQzPUB7LnohftLud4n4VvZMwpYm4K +Qct9PiSHjfCRVTwIB5Gsu6i3t18NMJtusgs8roxLeUylfFNdt2sWsCKBC1+NijUb+XB 4mns3yvj9QNClIoafZOcBMdkuRoYB2w9fNTa1J5mCH73w0OhFO+uHK1AHRr/Ve15WMdz ngDNUE+PQtHa5YJST3g6dN4210DeuagojgzEMIyH7uSOJKlv09WwbUe3C4ZR8BoygTAl s32A== X-Gm-Message-State: ANoB5pklWJtcFdPgSQq4tadp3V9VONdjO7KZaxHMMi5C071rXSYWG0Ck U3innLGTfNKVNTUWXbm2AgyjiQ1XunzGxyz4BSU= X-Google-Smtp-Source: AA0mqf7UskioN71UuDk6vjuVC/PW9/fS7kO0zwZN2hwwse7ddZz+mSeJJKKiVOkT+7TrdbFYpahPbqinvev4nKmjpGI= X-Received: by 2002:a67:e94e:0:b0:3a7:91c0:5915 with SMTP id p14-20020a67e94e000000b003a791c05915mr1071613vso.84.1669000264642; Sun, 20 Nov 2022 19:11:04 -0800 (PST) MIME-Version: 1.0 References: <20221109230718.3240479-1-philipp.tomsich@vrull.eu> <84ccfc10-df8c-5c77-913e-2819c7a14ee4@gmail.com> <966b3a77-5cda-c4d0-be4e-2083c502ba05@ventanamicro.com> In-Reply-To: <966b3a77-5cda-c4d0-be4e-2083c502ba05@ventanamicro.com> From: Kito Cheng Date: Mon, 21 Nov 2022 11:10:53 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Optimise adding a (larger than simm12) constant To: Jeff Law Cc: Philipp Tomsich , Jeff Law , gcc-patches@gcc.gnu.org, Christoph Muellner , Palmer Dabbelt , Vineet Gupta Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > @@ -464,6 +464,60 @@ > [(set_attr "type" "arith") > (set_attr "mode" "DI")]) > > +(define_expand "add3" > + [(set (match_operand:GPR 0 "register_operand" "=r,r") > + (plus:GPR (match_operand:GPR 1 "register_operand" " r,r") > + (match_operand:GPR 2 "addi_operand" " r,I")))] Is it possible to just define a predicate that accepts register_operand and CONST_INT_P, and then handle all cases in add3 pattern? My point is put all check in one place: e.g. check TARGET_ZBA && const_arith_shifted123_operand (operands[2], mode) in add3 rather than check TARGET_ZBA in addi_operand and use sh[123]add in add3 without check. and that also means we need to sync addi_opearnad and add3 once we have extension XX could improve addi codegen. > + "" > +{ > + if (arith_operand (operands[2], mode)) > + emit_insn (gen_riscv_add3 (operands[0], operands[1], operands[2])); > + else if (const_arith_2simm12_operand (operands[2], mode)) const_arith_2simm12_operand only used once, could you inline the condition here? > + { > + /* Split into two immediates that add up to the desired value: > + * e.g., break up "a + 2445" into: > + * addi a0,a0,2047 > + * addi a0,a0,398 > + */ > + > + HOST_WIDE_INT val = INTVAL (operands[2]); > + HOST_WIDE_INT saturated = HOST_WIDE_INT_M1U << (IMM_BITS - 1); > + > + if (val >= 0) > + saturated = ~saturated; > + > + val -= saturated; > + > + rtx tmp = gen_reg_rtx (mode); > + emit_insn (gen_riscv_add3 (tmp, operands[1], GEN_INT (saturated))); > + emit_insn (gen_riscv_add3 (operands[0], tmp, GEN_INT (val))); > + } > + else if (mode == word_mode > + && const_arith_shifted123_operand (operands[2], mode)) Same for const_arith_shifted123_operand. > + { > + /* Use a sh[123]add and an immediate shifted down by 1, 2, or 3. */ > + > + HOST_WIDE_INT val = INTVAL (operands[2]); > + int shamt = ctz_hwi (val); > + > + if (shamt > 3) > + shamt = 3; > + > + rtx tmp = gen_reg_rtx (mode); > + emit_insn (gen_rtx_SET (tmp, GEN_INT (val >> shamt))); > + > + /* We don't use gen_riscv_shNadd here, as it will only exist for > + . Instead we build up its canonical form directly. */ > + rtx shifted_imm = gen_rtx_ASHIFT (mode, tmp, GEN_INT (shamt)); > + rtx shNadd = gen_rtx_PLUS (mode, shifted_imm, operands[1]); > + emit_insn (gen_rtx_SET (operands[0], shNadd)); > + } > + else > + FAIL; Seems add3 FAIL will cause problems, we need either add something like: operands[2] = force_reg (mode, operands[2]); emit_insn (gen_rtx_SET (operands[0], gen_rtx_PLUS (mode, operands[1], operands[2]))); Or just gcc_unreachable () if we keep using addi_operand to guard this pattern.