From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2f.google.com (mail-vs1-xe2f.google.com [IPv6:2607:f8b0:4864:20::e2f]) by sourceware.org (Postfix) with ESMTPS id F335A3858D20 for ; Mon, 12 Jun 2023 12:37:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F335A3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2f.google.com with SMTP id ada2fe7eead31-43b1aa3ec78so1202187137.3 for ; Mon, 12 Jun 2023 05:37:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686573434; x=1689165434; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=rDJ4LbQZRghlp/Ma5FoTCU3I+b3bVVqDZkHrXAQu8vg=; b=FsIYQBdYE9OsTmct/EirotmZ9hvijzpoZs/vKgwPPxZ08nR/Y/lELCwXSMVVdCZrMZ XniDRrIkYrE/EfTvhO/W78ojbnO8N/k1IFfRvMrgX+a2TVQXpRMnMW8lSSSJeDlrRn5C RCqqXbh8ANBZh1Quss4yf9jKyLSijbQJUca8v36YolUVhl/n1xIlnq6n6l9Uh1OijPUw p7/nyemUD2lqP9AwrxUNgwJMN+J7b4mhffdt9tbdijbhNiHwT9jOBanoxW6O7q1e5sYf MY6n+OxcXPDoQUH2/s2bPNP60ay1tHodqvlU5+Yr5RvYfHO/xubjAocxYqS+jm+k25KT d03g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686573434; x=1689165434; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rDJ4LbQZRghlp/Ma5FoTCU3I+b3bVVqDZkHrXAQu8vg=; b=Ma63btm/JXGpfJlUgvfUquySB5tO5gLxol/NIsyvrxGFGmlVg9th3w9ToUkSwMhAlv IEzrNxx4B6FIE3ROWIDRPUQyKOxGc5Wp+Ps5CEEFc+YqFa/yXRy6XdfVGXWpGJ3rlvPl 1q6TTYhS9e72/D9LuisjzOuzfw/wOZ0nLetHAXXs7Run+HfTs/1SQ+JABUHX1/bmx6cz RJcFwCvPc9xh8lesYywH1UI5xyWvQOyKvYm8JptiOK8ux8gwr5CazMh3WQe4H+cDeTgk bixwpfH9y025D0qQpHRotONDjWnTAWIKDFMyH0YbFMsIIB8HStQ0FKgk4NQIJlR7Nbw+ LyWA== X-Gm-Message-State: AC+VfDwaxAvU01V4KbG9m7UoIncWRrtt1afXkY9GM3urm6YR70IYGCL2 hgj4JF9FL4sD/hJN/SeK3mIfsPW2L9cRAczHF8g= X-Google-Smtp-Source: ACHHUZ7oW8ZdaB5nLlKX1BSAUFtxD66wmQfVpdUO3lB2zCxo7/ZFQg1nFAMhju4q46AAZ7rhMlc0ez0D7jtMG+DWSSI= X-Received: by 2002:a67:f584:0:b0:43d:ed5a:ab29 with SMTP id i4-20020a67f584000000b0043ded5aab29mr1681789vso.1.1686573434140; Mon, 12 Jun 2023 05:37:14 -0700 (PDT) MIME-Version: 1.0 References: <20230612024102.580504-1-juzhe.zhong@rivai.ai> <318C0A4819375A25+2023061220253167608810@rivai.ai> In-Reply-To: <318C0A4819375A25+2023061220253167608810@rivai.ai> From: Kito Cheng Date: Mon, 12 Jun 2023 20:37:02 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization To: "juzhe.zhong@rivai.ai" Cc: gcc-patches , "Kito.cheng" , palmer , palmer , jeffreyalaw , Robin Dapp Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: We have two style predictor for those define_insn_and_split patterns, "TARGET_VECTOR"/"&& can_create_pseudo_p ()" and "TARGET_VECTOR && can_create_pseudo_p ()"/"&& 1", could you unify all to later form? I feel that would be safer since those patterns are really only valid before RA(can_create_pseudo_p() =3D=3D true), although it's mostly used by combine pass so it's mostly safe, but IMO we should fix this soon rather than fix that until we hit this later. OK for this patch as it is, and I would like to have a separated patch to fix all those issues. On Mon, Jun 12, 2023 at 8:27=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > Is this patch ok for trunk? > > > > juzhe.zhong@rivai.ai > > From: juzhe.zhong > Date: 2023-06-12 10:41 > To: gcc-patches > CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe= -Zhong > Subject: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectori= zation > From: Juzhe-Zhong > > Optimize the following auto-vectorization codes: > void foo (int16_t * __restrict a, int32_t * __restrict b, int32_t c, int = n) > { > for (int i =3D 0; i < n; i++) > a[i] =3D b[i] >> c; > } > > Before this patch: > foo: > ble a3,zero,.L5 > .L3: > vsetvli a5,a3,e32,m1,ta,ma > vle32.v v1,0(a1) > vsetvli a4,zero,e32,m1,ta,ma > vsra.vx v1,v1,a2 > vsetvli zero,zero,e16,mf2,ta,ma > slli a7,a5,2 > vncvt.x.x.w v1,v1 > slli a6,a5,1 > vsetvli zero,a5,e16,mf2,ta,ma > sub a3,a3,a5 > vse16.v v1,0(a0) > add a1,a1,a7 > add a0,a0,a6 > bne a3,zero,.L3 > .L5: > ret > > After this patch: > foo: > ble a3,zero,.L5 > .L3: > vsetvli a5,a3,e32,m1,ta,ma > vle32.v v1,0(a1) > vsetvli a7,zero,e16,mf2,ta,ma > slli a6,a5,2 > vnsra.wx v1,v1,a2 > slli a4,a5,1 > vsetvli zero,a5,e16,mf2,ta,ma > sub a3,a3,a5 > vse16.v v1,0(a0) > add a1,a1,a6 > add a0,a0,a4 > bne a3,zero,.L3 > .L5: > ret > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md (*vtrunc): New pattern. > (*trunc): Ditto. > * config/riscv/autovec.md (3): Change to define_insn= _and_split. > (v3): Ditto. > (trunc2): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: New test. > * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: New test. > * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: New test. > * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: New test. > * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: New test. > * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: New test. > > --- > gcc/config/riscv/autovec-opt.md | 46 +++++++++++++++++ > gcc/config/riscv/autovec.md | 43 ++++++++++------ > .../riscv/rvv/autovec/binop/narrow-1.c | 31 ++++++++++++ > .../riscv/rvv/autovec/binop/narrow-2.c | 32 ++++++++++++ > .../riscv/rvv/autovec/binop/narrow-3.c | 31 ++++++++++++ > .../riscv/rvv/autovec/binop/narrow_run-1.c | 50 +++++++++++++++++++ > .../riscv/rvv/autovec/binop/narrow_run-2.c | 46 +++++++++++++++++ > .../riscv/rvv/autovec/binop/narrow_run-3.c | 46 +++++++++++++++++ > 8 files changed, 311 insertions(+), 14 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narro= w-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narro= w-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narro= w-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narro= w_run-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narro= w_run-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narro= w_run-3.c > > diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-o= pt.md > index 7bb93eed220..aef28e445e1 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -330,3 +330,49 @@ > } > [(set_attr "type" "viwmuladd") > (set_attr "mode" "")]) > + > +;; ---------------------------------------------------------------------= ---- > +;; ---- [INT] Binary narrow shifts. > +;; ---------------------------------------------------------------------= ---- > +;; Includes: > +;; - vnsrl.wv/vnsrl.wx/vnsrl.wi > +;; - vnsra.wv/vnsra.wx/vnsra.wi > +;; ---------------------------------------------------------------------= ---- > + > +(define_insn_and_split "*vtrunc" > + [(set (match_operand: 0 "register_operand" "=3Dv= r,vr") > + (truncate: > + (any_shiftrt:VWEXTI > + (match_operand:VWEXTI 1 "register_operand" " vr,= vr") > + (any_extend:VWEXTI > + (match_operand: 2 "vector_shift_operand" " vr,= vk")))))] > + "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + [(const_int 0)] > +{ > + insn_code icode =3D code_for_pred_narrow (, mo= de); > + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operand= s); > + DONE; > +} > + [(set_attr "type" "vnshift") > + (set_attr "mode" "")]) > + > +(define_insn_and_split "*trunc" > + [(set (match_operand: 0 "register_operand" "=3Dvr") > + (truncate: > + (any_shiftrt:VWEXTI > + (match_operand:VWEXTI 1 "register_operand" " vr") > + (match_operand: 2 "csr_operand" " rK"))))] > + "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + [(const_int 0)] > +{ > + operands[2] =3D gen_lowpart (Pmode, operands[2]); > + insn_code icode =3D code_for_pred_narrow_scalar (, <= MODE>mode); > + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operand= s); > + DONE; > +} > + [(set_attr "type" "vnshift") > + (set_attr "mode" "")]) > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index b7070099f29..eadc2c5b595 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -150,18 +150,23 @@ > ;; - vsll.vi/vsra.vi/vsrl.vi > ;; ----------------------------------------------------------------------= --- > -(define_expand "3" > - [(set (match_operand:VI 0 "register_operand") > +(define_insn_and_split "3" > + [(set (match_operand:VI 0 "register_operand" "=3Dvr") > (any_shift:VI > - (match_operand:VI 1 "register_operand") > - (match_operand: 2 "csr_operand")))] > + (match_operand:VI 1 "register_operand" " vr") > + (match_operand: 2 "csr_operand" " rK")))] > "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + [(const_int 0)] > { > operands[2] =3D gen_lowpart (Pmode, operands[2]); > riscv_vector::emit_vlmax_insn (code_for_pred_scalar (, mod= e), > riscv_vector::RVV_BINOP, operands); > DONE; > -}) > +} > + [(set_attr "type" "vshift") > + (set_attr "mode" "")]) > ;; ----------------------------------------------------------------------= --- > ;; ---- [INT] Binary shifts by scalar. > @@ -170,17 +175,22 @@ > ;; - vsll.vv/vsra.vv/vsrl.vv > ;; ----------------------------------------------------------------------= --- > -(define_expand "v3" > - [(set (match_operand:VI 0 "register_operand") > +(define_insn_and_split "v3" > + [(set (match_operand:VI 0 "register_operand" "=3Dvr,vr") > (any_shift:VI > - (match_operand:VI 1 "register_operand") > - (match_operand:VI 2 "vector_shift_operand")))] > + (match_operand:VI 1 "register_operand" " vr,vr") > + (match_operand:VI 2 "vector_shift_operand" " vr,vk")))] > "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + [(const_int 0)] > { > riscv_vector::emit_vlmax_insn (code_for_pred (, mode), > riscv_vector::RVV_BINOP, operands); > DONE; > -}) > +} > + [(set_attr "type" "vshift") > + (set_attr "mode" "")]) > ;; ----------------------------------------------------------------------= --- > ;; ---- [BOOL] Binary logical operations > @@ -395,16 +405,21 @@ > ;; ----------------------------------------------------------------------= --- > ;; - vncvt.x.x.w > ;; ----------------------------------------------------------------------= --- > -(define_expand "trunc2" > - [(set (match_operand: 0 "register_operand") > +(define_insn_and_split "trunc2" > + [(set (match_operand: 0 "register_operand" "=3Dvr") > (truncate: > - (match_operand:VWEXTI 1 "register_operand")))] > + (match_operand:VWEXTI 1 "register_operand" " vr")))] > "TARGET_VECTOR" > + "#" > + "&& can_create_pseudo_p ()" > + [(const_int 0)] > { > insn_code icode =3D code_for_pred_trunc (mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands= ); > DONE; > -}) > +} > + [(set_attr "type" "vshift") > + (set_attr "mode" "")]) > ;; ----------------------------------------------------------------------= --- > ;; Truncation to a mode whose inner mode size is a quarter of mode's. > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c > new file mode 100644 > index 00000000000..3de8d85b52d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define TEST_TYPE(TYPE1, TYPE2) = \ > + __attribute__ ((noipa)) void vnshift_##TYPE1##_##TYPE2 ( = \ > + TYPE2 *__restrict dst, TYPE1 *__restrict a, TYPE2 *__restrict b, int= n) \ > + { = \ > + for (int i =3D 0; i < n; i++) = \ > + dst[i] =3D a[i] >> b[i]; = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int16_t, int8_t) = \ > + TEST_TYPE (int16_t, uint8_t) = \ > + TEST_TYPE (uint16_t, int8_t) = \ > + TEST_TYPE (uint16_t, uint8_t) = \ > + TEST_TYPE (int32_t, int16_t) = \ > + TEST_TYPE (int32_t, uint16_t) = \ > + TEST_TYPE (uint32_t, int16_t) = \ > + TEST_TYPE (uint32_t, uint16_t) = \ > + TEST_TYPE (int64_t, int32_t) = \ > + TEST_TYPE (int64_t, uint32_t) = \ > + TEST_TYPE (uint64_t, int32_t) = \ > + TEST_TYPE (uint64_t, uint32_t) > + > +TEST_ALL () > + > +/* { dg-final { scan-assembler-times {\tvnsra\.wv} 6 } } */ > +/* { dg-final { scan-assembler-times {\tvnsrl\.wv} 5 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c > new file mode 100644 > index 00000000000..e5c2e37f5fa > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv32gcv -mabi=3Dilp32d --param=3Dri= scv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define TEST_TYPE(TYPE1, TYPE2) = \ > + __attribute__ (( = \ > + noipa)) void vnshift_##TYPE1##_##TYPE2 (TYPE2 *__restrict dst, = \ > + TYPE1 *__restrict a, int n) \ > + { = \ > + for (int i =3D 0; i < n; i++) = \ > + dst[i] =3D a[i] >> 7; = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int16_t, int8_t) = \ > + TEST_TYPE (int16_t, uint8_t) = \ > + TEST_TYPE (uint16_t, int8_t) = \ > + TEST_TYPE (uint16_t, uint8_t) = \ > + TEST_TYPE (int32_t, int16_t) = \ > + TEST_TYPE (int32_t, uint16_t) = \ > + TEST_TYPE (uint32_t, int16_t) = \ > + TEST_TYPE (uint32_t, uint16_t) = \ > + TEST_TYPE (int64_t, int32_t) = \ > + TEST_TYPE (int64_t, uint32_t) = \ > + TEST_TYPE (uint64_t, int32_t) = \ > + TEST_TYPE (uint64_t, uint32_t) > + > +TEST_ALL () > + > +/* { dg-final { scan-assembler-times {\tvnsra\.wi} 6 } } */ > +/* { dg-final { scan-assembler-times {\tvnsrl\.wi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c > new file mode 100644 > index 00000000000..3b288466394 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=3Drv64gcv -mabi=3Dlp64d --param=3Dris= cv-autovec-preference=3Dscalable" } */ > + > +#include > + > +#define TEST_TYPE(TYPE1, TYPE2) = \ > + __attribute__ ((noipa)) void vnshift_##TYPE1##_##TYPE2 ( = \ > + TYPE2 *__restrict dst, TYPE1 *__restrict a, TYPE2 b, int n) = \ > + { = \ > + for (int i =3D 0; i < n; i++) = \ > + dst[i] =3D a[i] >> b; = \ > + } > + > +#define TEST_ALL() = \ > + TEST_TYPE (int16_t, int8_t) = \ > + TEST_TYPE (int16_t, uint8_t) = \ > + TEST_TYPE (uint16_t, int8_t) = \ > + TEST_TYPE (uint16_t, uint8_t) = \ > + TEST_TYPE (int32_t, int16_t) = \ > + TEST_TYPE (int32_t, uint16_t) = \ > + TEST_TYPE (uint32_t, int16_t) = \ > + TEST_TYPE (uint32_t, uint16_t) = \ > + TEST_TYPE (int64_t, int32_t) = \ > + TEST_TYPE (int64_t, uint32_t) = \ > + TEST_TYPE (uint64_t, int32_t) = \ > + TEST_TYPE (uint64_t, uint32_t) > + > +TEST_ALL () > + > +/* { dg-final { scan-assembler-times {\tvnsra\.wx} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvnsrl\.wx} 4 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-= 1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c > new file mode 100644 > index 00000000000..2a898104fa8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c > @@ -0,0 +1,50 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include > +#include "narrow-1.c" > + > +#define RUN(TYPE1, TYPE2, SZ) = \ > + TYPE1 a##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + TYPE2 b##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + TYPE2 dst##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + for (int i =3D 0; i < SZ; i++) = \ > + { = \ > + a##TYPE1##_##TYPE2##_##SZ[i] =3D i % 8723; = \ > + b##TYPE1##_##TYPE2##_##SZ[i] =3D i % (sizeof (TYPE2) * 3); = \ > + } = \ > + vnshift_##TYPE1##_##TYPE2 (dst##TYPE1##_##TYPE2##_##SZ, = \ > + a##TYPE1##_##TYPE2##_##SZ, \ > + b##TYPE1##_##TYPE2##_##SZ, SZ); \ > + for (int i =3D 0; i < SZ; i++) = \ > + { = \ > + assert (dst##TYPE1##_##TYPE2##_##SZ[i] = \ > + =3D=3D (TYPE2) (a##TYPE1##_##TYPE2##_##SZ[i] = \ > + >> b##TYPE1##_##TYPE2##_##SZ[i])); \ > + } > + > +#define RUN_ALL(SZ) = \ > + RUN (int16_t, int8_t, SZ) = \ > + RUN (int16_t, uint8_t, SZ) = \ > + RUN (uint16_t, int8_t, SZ) = \ > + RUN (uint16_t, uint8_t, SZ) = \ > + RUN (int32_t, int16_t, SZ) = \ > + RUN (int32_t, uint16_t, SZ) = \ > + RUN (uint32_t, int16_t, SZ) = \ > + RUN (uint32_t, uint16_t, SZ) = \ > + RUN (int64_t, int32_t, SZ) = \ > + RUN (int64_t, uint32_t, SZ) = \ > + RUN (uint64_t, int32_t, SZ) = \ > + RUN (uint64_t, uint32_t, SZ) > + > +int > +main () > +{ > + RUN_ALL (15) > + RUN_ALL (16) > + RUN_ALL (17) > + RUN_ALL (127) > + RUN_ALL (128) > + RUN_ALL (129) > + RUN_ALL (512) > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-= 2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c > new file mode 100644 > index 00000000000..1630ba1a5f8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c > @@ -0,0 +1,46 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include > +#include "narrow-2.c" > + > +#define RUN(TYPE1, TYPE2, SZ) = \ > + TYPE1 a##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + TYPE2 dst##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + for (int i =3D 0; i < SZ; i++) = \ > + { = \ > + a##TYPE1##_##TYPE2##_##SZ[i] =3D i % 8723; = \ > + } = \ > + vnshift_##TYPE1##_##TYPE2 (dst##TYPE1##_##TYPE2##_##SZ, = \ > + a##TYPE1##_##TYPE2##_##SZ, SZ); \ > + for (int i =3D 0; i < SZ; i++) = \ > + { = \ > + assert (dst##TYPE1##_##TYPE2##_##SZ[i] = \ > + =3D=3D (TYPE2) (a##TYPE1##_##TYPE2##_##SZ[i] >> 7)); = \ > + } > + > +#define RUN_ALL(SZ) = \ > + RUN (int16_t, int8_t, SZ) = \ > + RUN (int16_t, uint8_t, SZ) = \ > + RUN (uint16_t, int8_t, SZ) = \ > + RUN (uint16_t, uint8_t, SZ) = \ > + RUN (int32_t, int16_t, SZ) = \ > + RUN (int32_t, uint16_t, SZ) = \ > + RUN (uint32_t, int16_t, SZ) = \ > + RUN (uint32_t, uint16_t, SZ) = \ > + RUN (int64_t, int32_t, SZ) = \ > + RUN (int64_t, uint32_t, SZ) = \ > + RUN (uint64_t, int32_t, SZ) = \ > + RUN (uint64_t, uint32_t, SZ) > + > +int > +main () > +{ > + RUN_ALL (15) > + RUN_ALL (16) > + RUN_ALL (17) > + RUN_ALL (127) > + RUN_ALL (128) > + RUN_ALL (129) > + RUN_ALL (512) > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-= 3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c > new file mode 100644 > index 00000000000..7638851e4fa > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c > @@ -0,0 +1,46 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "--param=3Driscv-autovec-preference=3Dscalabl= e" } */ > + > +#include > +#include "narrow-3.c" > + > +#define RUN(TYPE1, TYPE2, SZ) = \ > + TYPE1 a##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + TYPE2 dst##TYPE1##_##TYPE2##_##SZ[SZ]; = \ > + for (int i =3D 0; i < SZ; i++) = \ > + { = \ > + a##TYPE1##_##TYPE2##_##SZ[i] =3D i % 8723; = \ > + } = \ > + vnshift_##TYPE1##_##TYPE2 (dst##TYPE1##_##TYPE2##_##SZ, = \ > + a##TYPE1##_##TYPE2##_##SZ, 9, SZ); \ > + for (int i =3D 0; i < SZ; i++) = \ > + { = \ > + assert (dst##TYPE1##_##TYPE2##_##SZ[i] = \ > + =3D=3D (TYPE2) (a##TYPE1##_##TYPE2##_##SZ[i] >> 9)); = \ > + } > + > +#define RUN_ALL(SZ) = \ > + RUN (int16_t, int8_t, SZ) = \ > + RUN (int16_t, uint8_t, SZ) = \ > + RUN (uint16_t, int8_t, SZ) = \ > + RUN (uint16_t, uint8_t, SZ) = \ > + RUN (int32_t, int16_t, SZ) = \ > + RUN (int32_t, uint16_t, SZ) = \ > + RUN (uint32_t, int16_t, SZ) = \ > + RUN (uint32_t, uint16_t, SZ) = \ > + RUN (int64_t, int32_t, SZ) = \ > + RUN (int64_t, uint32_t, SZ) = \ > + RUN (uint64_t, int32_t, SZ) = \ > + RUN (uint64_t, uint32_t, SZ) > + > +int > +main () > +{ > + RUN_ALL (15) > + RUN_ALL (16) > + RUN_ALL (17) > + RUN_ALL (127) > + RUN_ALL (128) > + RUN_ALL (129) > + RUN_ALL (512) > +} > -- > 2.36.3 > >