committed, thanks :)

On Mon, Jan 23, 2023 at 3:29 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:

>
>
> On 1/20/23 02:33, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > According to RVV ISA, RVV doesn't support EEW == 64 vector type for
> zve32x
> > and zve32f. So it makes sense add predicate in the iterators of EEW = 64
> > vector modes.
> >
> > gcc/ChangeLog:
> >
> >          * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32
> predicates.
> OK.
>
> Jeff
>