From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92f.google.com (mail-ua1-x92f.google.com [IPv6:2607:f8b0:4864:20::92f]) by sourceware.org (Postfix) with ESMTPS id CB9A33858414 for ; Thu, 11 May 2023 11:10:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB9A33858414 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x92f.google.com with SMTP id a1e0cc1a2514c-77d46c7dd10so40683896241.0 for ; Thu, 11 May 2023 04:10:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683803421; x=1686395421; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=JNobtdwiwYD8AChdDd/+hFjfFjnWSzr5LfWLgyrHmEM=; b=Sl9RjmYTWw2e9bBY7rNzTuCYn4qybVftL1pbk/MGKP3frHSleH3bLhe0cdp9Yah+Vs FOXYrMB1c01Dl1tM2uqZj8yRUtwfKtsN+czAUkJvklw22s5/gSKoBNPT8jVfObhiMxBL VlDlkk2iKWiHTGQ0XdZzhQrBihxZr44FdKMqQwt/oOoCPXNK2xs7Iv13QpVyfzw2PQ2M Yo7rHkfsSnEGxoH35qogsrV/UnRSdUXT1fPDNmXsWyo5CwEttfPxkycz/PaNW1SF6VBw QOowom/o22MxcjZQ8HyJP1rJ2z+yrA0otwEyP57cLlUsJLX1w8c0kCYItapGY0e0Mbt+ E3Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683803421; x=1686395421; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JNobtdwiwYD8AChdDd/+hFjfFjnWSzr5LfWLgyrHmEM=; b=eQ5Zsq+mcojxH3eOgPMwDYo3tBHkIrqQU0Xc/BkooTLyyznCq04YXZJcmItiUVmpGs 6fhbjEqT4LfiVJyziEZkrbdNHryaoDiE5yST1ZI9POAsvcbbeP7oGU0uroK8quor7LXF 2BbvxyWbkILAV877MsgAAWRfsVca6YzcF+s73VDpzwHeYB/E/II1NmWxsYnZnKUSwGqe qRoitEDNHXiyYhRdWismNYFC4XgYWp8uELoCtzSbk2+OF3KcxQSQfdI/uUlPXCNJ86ex LF0olCHVPEnhBjHFz59HvUl5jR5Yv0csG5m4mAP8UiCLwXLYmxiz2PTEy5cTLqXBqSDW EEbg== X-Gm-Message-State: AC+VfDwgTXFJ1+dqCKYia72KNe2FlBLjXDrz5UfU6ZrDqf1s7EMTGyey 2EUfiwcb6PnLQGggK0o7/IS254uzm4vJJ++nAI7Nx5rR X-Google-Smtp-Source: ACHHUZ717qKuLwU0Hk8BAUplI1s+QAJYowCqSBHCQPhSZhTAO6RE2pR+VGdCmCzum0MD+kVagr+eCE1kA6vIj3whexQ= X-Received: by 2002:a05:6102:4b9:b0:436:247c:d3d4 with SMTP id r25-20020a05610204b900b00436247cd3d4mr1596497vsa.7.1683803420802; Thu, 11 May 2023 04:10:20 -0700 (PDT) MIME-Version: 1.0 References: <22063fee-8e38-6da4-8658-4e7c80a3199e@gmail.com> <3D528D4EC594F954+20230511183542481340220@rivai.ai> In-Reply-To: <3D528D4EC594F954+20230511183542481340220@rivai.ai> From: Kito Cheng Date: Thu, 11 May 2023 19:10:08 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: Split off shift patterns for autovectorization. To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: Robin Dapp , palmer , gcc-patches , collison , jeffreyalaw Content-Type: multipart/alternative; boundary="000000000000c4c2dd05fb6908c7" X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000c4c2dd05fb6908c7 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks, LGTM juzhe.zhong@rivai.ai =E6=96=BC 2023=E5=B9=B45=E6=9C= =8811=E6=97=A5 =E9=80=B1=E5=9B=9B 18:37 =E5=AF=AB=E9=81=93=EF=BC=9A > LGTM. Plz commit it now. Then I can rebase vec_init patch. > > > > juzhe.zhong@rivai.ai > > From: Robin Dapp > Date: 2023-05-11 18:33 > To: Palmer Dabbelt > CC: gcc-patches; juzhe.zhong; Kito Cheng; collison; jeffreyalaw; rdapp.gcc > Subject: [PATCH v2] RISC-V: Split off shift patterns for autovectorizatio= n. > > "csr_operand" does seem wrong, though, as that just accepts constants. > > Maybe "arith_operand" is the way to go? I haven't looked at the > > V immediates though. > > I was pondering changing the shift-count operand to QImode everywhere > but that indeed does not help code generation across the board. It can > still work but might require extra patterns here and there. > > "csr_operand" accepts 0-31 constants as well as registers which should > be fine here. > > No changes from v1 apart from the RISC-V in the subject and a bit of > rebasing and comments. > > > This patch splits off the shift patterns of the binop patterns. > This is necessary as the scalar shifts require a Pmode operand > as shift count. To this end, a new iterator any_int_binop_no_shift > is introduced. At a later point when the binops are split up > further in commutative and non-commutative patterns (which both > do not include the shift patterns) we might not need this anymore. > > gcc/ChangeLog: > > * config/riscv/autovec.md (3): Add scalar shift > pattern. > (v3): Add vector shift pattern. > * config/riscv/vector-iterators.md: New iterator. > --- > gcc/config/riscv/autovec.md | 47 +++++++++++++++++++++++++++- > gcc/config/riscv/vector-iterators.md | 4 +++ > 2 files changed, 50 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 58926ed3e67..ac0c939d277 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -97,7 +97,7 @@ (define_expand "@vec_series" > (define_expand "3" > [(set (match_operand:VI 0 "register_operand") > - (any_int_binop:VI > + (any_int_binop_no_shift:VI > (match_operand:VI 1 "") > (match_operand:VI 2 "")))] > "TARGET_VECTOR" > @@ -119,3 +119,48 @@ (define_expand "3" > NULL, mode); > DONE; > }) > + > +;; > ------------------------------------------------------------------------- > +;; ---- [INT] Binary shifts by scalar. > +;; > ------------------------------------------------------------------------- > +;; Includes: > +;; - vsll.vx/vsra.vx/vsrl.vx > +;; - vsll.vi/vsra.vi/vsrl.vi > +;; > ------------------------------------------------------------------------- > + > +(define_expand "3" > + [(set (match_operand:VI 0 "register_operand") > + (any_shift:VI > + (match_operand:VI 1 "register_operand") > + (match_operand: 2 "csr_operand")))] > + "TARGET_VECTOR" > +{ > + if (!CONST_SCALAR_INT_P (operands[2])) > + operands[2] =3D gen_lowpart (Pmode, operands[2]); > + riscv_vector::emit_len_binop (code_for_pred_scalar > + (, mode), > + operands[0], operands[1], operands[2], > + NULL_RTX, mode, Pmode); > + DONE; > +}) > + > +;; > ------------------------------------------------------------------------- > +;; ---- [INT] Binary shifts by scalar. > +;; > ------------------------------------------------------------------------- > +;; Includes: > +;; - vsll.vv/vsra.vv/vsrl.vv > +;; > ------------------------------------------------------------------------- > + > +(define_expand "v3" > + [(set (match_operand:VI 0 "register_operand") > + (any_shift:VI > + (match_operand:VI 1 "register_operand") > + (match_operand:VI 2 "vector_shift_operand")))] > + "TARGET_VECTOR" > +{ > + riscv_vector::emit_len_binop (code_for_pred > + (, mode), > + operands[0], operands[1], operands[2], > + NULL_RTX, mode); > + DONE; > +}) > diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index 29c9d77674b..5cf958ba845 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -1409,6 +1409,10 @@ (define_code_iterator any_commutative_binop [plus > and ior xor > (define_code_iterator any_non_commutative_binop [minus div udiv mod umod]) > +(define_code_iterator any_int_binop_no_shift > + [plus minus and ior xor smax umax smin umin mult div udiv mod umod > +]) > + > (define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus > us_minus]) > (define_code_iterator sat_int_plus_binop [ss_plus us_plus]) > (define_code_iterator sat_int_minus_binop [ss_minus us_minus]) > -- > 2.40.0 > > > --000000000000c4c2dd05fb6908c7--