From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id 01A8D3858C20 for ; Mon, 22 Aug 2022 08:47:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 01A8D3858C20 Received: by mail-ej1-x629.google.com with SMTP id n7so1600166ejh.2 for ; Mon, 22 Aug 2022 01:47:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=GlkkkB0dVBeuR+0+Wm7+h6mjvdDPj1wjMe9yzVVsxvU=; b=zs2XCbqSEkByET9NfYs3WEgg6ouXjVScR+Fa/Ac2tx3T4zHbAwyLi8uqNjO7TaXWIH Wb+rsdDuLPD4+FTyvER03uLcC+W3ANSsubR4WlfR4ezPO5H5T7xqfa8gs/2yyN25Y/r6 F2A2XRcADoyKiQAABU5D+KZpe1vu//G2BSa2CzwRJM4Vua82dLfSApSeauA3Lc12YjgC mfHlngdhrN7v7hHHF+TsKY2jl0HhONXC3kBHx51X+L3lZalT7784+fK4kR3EQDckfLqT vH7spYvIVbcKhP10gJjZpaIIwMAokP/OsGuhXeaik6rOz3RLjEZBzcZ1BkSilEkTCvMX N7SQ== X-Gm-Message-State: ACgBeo2E+eHJpZ1DMun353IEIcEORHQjhifMbOHq0F5GOQOFD6pcj/95 6q2xUAa3USTl2aayU8h9quZj+WB2yPcu7YSFHvo= X-Google-Smtp-Source: AA6agR4gQwDLBRc6DVe6lYg7oAB3dhIXzLsBU5Ym2DtLfZirvlzLiC/wNvpS0J4ERWRzDCyoefflWd8IE3/fRJbhPoc= X-Received: by 2002:a17:906:ef90:b0:730:9cd8:56d7 with SMTP id ze16-20020a170906ef9000b007309cd856d7mr11428377ejb.94.1661158066310; Mon, 22 Aug 2022 01:47:46 -0700 (PDT) MIME-Version: 1.0 References: <1660860233-11175-1-git-send-email-apinski@marvell.com> <1660860233-11175-7-git-send-email-apinski@marvell.com> In-Reply-To: <1660860233-11175-7-git-send-email-apinski@marvell.com> From: Kito Cheng Date: Mon, 22 Aug 2022 16:47:34 +0800 Message-ID: Subject: Re: [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns To: apinski@marvell.com Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Aug 2022 08:47:49 -0000 I know using more precise constraints might result in better code gen in some situations, but I am Curious what's the difference between the using pattern condition and constraints/predicates in this case? Is there any performance or code gen difference? On Fri, Aug 19, 2022 at 6:07 AM apinski--- via Gcc-patches wrote: > > From: Andrew Pinski > > This simplifies the code by adding a predicate and a constraint for 1/2/3. > The aarch64 backend has a similar predicate called aarch64_shift_imm_ > which they use there. > > OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions. > > Thanks, > Andrew Pinski > > gcc/ChangeLog: > > * config/riscv/constraints.md (Ds3): New constraint. > * config/riscv/predicates.md (imm123_operand): New predicate. > * config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand. > (*shNadduw): Likewise. > --- > gcc/config/riscv/bitmanip.md | 8 +++----- > gcc/config/riscv/constraints.md | 6 ++++++ > gcc/config/riscv/predicates.md | 5 +++++ > 3 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index ebd6eee1a22..73a36f7751b 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -32,10 +32,9 @@ (define_insn "*zero_extendsidi2_bitmanip" > (define_insn "*shNadd" > [(set (match_operand:X 0 "register_operand" "=r") > (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") > - (match_operand:QI 2 "immediate_operand" "I")) > + (match_operand:QI 2 "imm123_operand" "Ds3")) > (match_operand:X 3 "register_operand" "r")))] > - "TARGET_ZBA > - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" > + "TARGET_ZBA" > "sh%2add\t%0,%1,%3" > [(set_attr "type" "bitmanip") > (set_attr "mode" "")]) > @@ -44,11 +43,10 @@ (define_insn "*shNadduw" > [(set (match_operand:DI 0 "register_operand" "=r") > (plus:DI > (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") > - (match_operand:QI 2 "immediate_operand" "I")) > + (match_operand:QI 2 "imm123_operand" "Ds3")) > (match_operand 3 "immediate_operand" "")) > (match_operand:DI 4 "register_operand" "r")))] > "TARGET_64BIT && TARGET_ZBA > - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) > && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" > "sh%2add.uw\t%0,%1,%4" > [(set_attr "type" "bitmanip") > diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md > index bafa4188ccb..61b84875fd9 100644 > --- a/gcc/config/riscv/constraints.md > +++ b/gcc/config/riscv/constraints.md > @@ -54,6 +54,12 @@ (define_constraint "L" > (and (match_code "const_int") > (match_test "LUI_OPERAND (ival)"))) > > +(define_constraint "Ds3" > + "@internal > + 1, 2 or 3 immediate" > + (and (match_code "const_int") > + (match_test "IN_RANGE (ival, 1, 3)"))) > + > ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is > ;; not available in RV32. > (define_constraint "G" > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 79e0c1d5589..2af7f661d6f 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -244,6 +244,11 @@ (define_predicate "imm5_operand" > (and (match_code "const_int") > (match_test "INTVAL (op) < 5"))) > > +;; A const_int for sh1add/sh2add/sh3add > +(define_predicate "imm123_operand" > + (and (match_code "const_int") > + (match_test "IN_RANGE (INTVAL (op), 1, 3)"))) > + > ;; A CONST_INT operand that consists of a single run of consecutive set bits. > (define_predicate "consecutive_bits_operand" > (match_code "const_int") > -- > 2.27.0 >