From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2e.google.com (mail-vs1-xe2e.google.com [IPv6:2607:f8b0:4864:20::e2e]) by sourceware.org (Postfix) with ESMTPS id 7E9F23858D1E for ; Mon, 19 Dec 2022 15:06:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7E9F23858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2e.google.com with SMTP id b189so8918908vsc.10 for ; Mon, 19 Dec 2022 07:06:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=EGDFjV67fTCXtf/nRv5DFXA9M2PiTDdFWV3wto6Du1k=; b=BNS4H+eH+FMNaLl3+svkiCuRbh6ulu4RuxoRGpjLltXDa1qddzNughY7EaooY2/3PB hsRinVV40rGPiAVxALQkfjDW7ed5xxN3tVkHz5J6ThGOKX6TR3Qxmkw3QTTaUF9t1gaC 1F9i4V0/G0vtwkgSaqFQL0gwOOQY9IIJUi8gcr+/wqUf+XpnwQHY0u69rktXJGZXbz5d EdmAqdNcCzuN8D5hz4e0G+Wj2vkYNbxvDsk4MtTAp/a5Z/h+3IOsc4s7EJFUR2Mnksky 2YaiBd/rzFueFZh5GLQaGTWjJN79/QKVrGJXrMNdfFXnlsXVxHA5lnO68DxNfx9BIq95 xoFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=EGDFjV67fTCXtf/nRv5DFXA9M2PiTDdFWV3wto6Du1k=; b=0vyxE8FuOuAoZ68C1F4J6rsccmq1d/FATxVafgFYvHw5fbKvtYmHgxWodcCBZJh5bV viULXrRXkGAPzYJDbUTKdMOo3Ine6TUsZ7OdewU84+kxifRFLi8TytozWZERFoQkDZ50 HDsvtHkRxI/phVhMpspMbs1EgOMUbekHb+RplgqOXYN/8JvcJrmufMehy1SICuPRfqrv z/XSDgewfgiNJ/thnA5b6KuOZ1O3vGv+W3yD867gvY+Dsd40BsWTPnsHFrDEWhXc/Rvx Kn+BK4mFDfdzVAe4+4lnQj+lVABj0GaJw51vQO9oa20Izmk/VHzD0R8ePcu6MlHr+Hn4 lpgg== X-Gm-Message-State: ANoB5ply2sAUHrE3JHc+CKzMDPDz14jicn8mqU8mKeg6Kvs9zNprfC7r p/tSHYT/8xAtSlvBPzvwFvRmMzUzaohI/TawXUs= X-Google-Smtp-Source: AA0mqf7xV1F6bpRhy1FIw4zddo+AyJtJ1Dp7VvR7UrtF1cosQmAgr6P/BTqCn3dex0QWhcN2wpOI2h2o1kb63dFK4KM= X-Received: by 2002:a67:f2c4:0:b0:3b0:f932:5a40 with SMTP id a4-20020a67f2c4000000b003b0f9325a40mr21717015vsn.30.1671462371423; Mon, 19 Dec 2022 07:06:11 -0800 (PST) MIME-Version: 1.0 References: <20221214070156.37689-1-juzhe.zhong@rivai.ai> In-Reply-To: From: Kito Cheng Date: Mon, 19 Dec 2022 23:05:58 +0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: Jeff Law , gcc-patches , palmer Content-Type: multipart/alternative; boundary="000000000000e77c2c05f02fa831" X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000e77c2c05f02fa831 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Commited to trunk. =E9=92=9F=E5=B1=85=E5=93=B2 =E6=96=BC 2022=E5=B9=B41= 2=E6=9C=8817=E6=97=A5 =E9=80=B1=E5=85=AD 09:52 =E5=AF=AB=E9=81=93=EF=BC=9A > Actually, I don't check and test HF carefully since I disable them. > Kito ask me to disable all HF modes since zvfhmin is no ratified and GCC > doesn't allow any un-ratified ISA. You can see vector-iterator.md that all > RVV modes supported including QI HI SI DI SF DF excluding HF and BF. > > > > juzhe.zhong@rivai.ai > > From: Jeff Law > Date: 2022-12-17 09:48 > To: juzhe.zhong; gcc-patches > CC: kito.cheng; palmer > Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration > > > On 12/14/22 00:01, juzhe.zhong@rivai.ai wrote: > > From: Ju-Zhe Zhong > > > > The attribute configuration of each machine mode are support in the > previous patch. > > I noticed some of them are not correct during VSETVL PASS testsing. > > Correct them in the single patch now. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-vector-switch.def (ENTRY): Correct > attributes. > > > > > > > @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32) > > ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64) > > > > /* TODO:Disable all FP16 vector, enable them when 'zvfh' is > supported. */ > > -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0) > > +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2) > Is there any value in making VNx32HF dependent on TARGET_MIN_VLEN > 32 > like we're doing for VNx32HI? In the past I've found it useful to have > HI, HF, BF behave identically as much as possible. > > You call. The patch is OK either way. > > jeff > > > > > --000000000000e77c2c05f02fa831--