From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe29.google.com (mail-vs1-xe29.google.com [IPv6:2607:f8b0:4864:20::e29]) by sourceware.org (Postfix) with ESMTPS id 3C6E63858C50 for ; Wed, 3 May 2023 10:59:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C6E63858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe29.google.com with SMTP id ada2fe7eead31-430192c84a1so1862596137.1 for ; Wed, 03 May 2023 03:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683111558; x=1685703558; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=qwdiicRQDJyBmlnSelMt5l5JrRG9U0rcjigVU5clz7s=; b=BrOmlOAl3/THVYxAesGq3Jy1XBIayzcAGbg0VUGI9EWZvvlRIxcjVzZGwKAwUgYH2+ oxmvQWYDtgJObmvyTrmY0jxpQH+0OHKhLud37AcxDN85b9Fdv3EHpIzadT/gVZnMVDXB XZ/UZnR8ZbxH39HbHkaXBIjqvVh4v8McwbY9CAbjc43VCkfK/tAMXhQnFQx78Mp+qZUB 2NG1+lJiR1+DudrsghNHYTUoqIkwo5OmwnMlYMvOYB8zjI34M+6XnWJDPzoAmh7sIREh qPzH1QKMfuJD6b0mayiGxJWNybIXQd2LK0IFwUbt4QpJS5WyLvrRZ959Q9AjCEfgSTne NHjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683111558; x=1685703558; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qwdiicRQDJyBmlnSelMt5l5JrRG9U0rcjigVU5clz7s=; b=UNmfLtcEQVFwFHPfS67MW9o5B+q+6lFzcKD3Cqb+wSDQBhK7dBtBUQnQ5uWyGcPwyS uFq2BDji+2v9Yxsb8Rjh/ld9rIC02esUpauopMbDM4Zur/NkGmXRqZGrdJwra91X9/3K 2NJV5hwntj+n3iuGxH1DGFo9aU1kOQAw1vDh8rUSZ/h//BEGDVU2t+1h3MYNhut/p5Ps 8rfH7eOiZG36E/6nTS5ozRv1WUljEBfcXyOpFUMjb8dnsWeVNgQZmtrQ1FGhPPK3THjA JvicphgYOniqPc6Emx8T6Tm/T4tQK+ZVfALpY6+r2RD5X4K+wLRdKwOaSQ5m6sy9oGU3 zqaw== X-Gm-Message-State: AC+VfDwl/7syyOiT23858+aSglfC3HkWd0V9slKyqks6aUi33MbZ9GBr qYlwyjQGAzlGsKdKsHLNncbap6tfTPmL21eguBLlaR7MidJ8jw== X-Google-Smtp-Source: ACHHUZ7Qvi+IWTVdSCCkBusN1Eemu3vD4NLePqQIVuCvf+2wUrKYcpvRw81dsQso9vOs+fgCsBAKGDyuyebWqVhp3d4= X-Received: by 2002:a67:fb11:0:b0:42e:38c1:8a54 with SMTP id d17-20020a67fb11000000b0042e38c18a54mr1163830vsr.0.1683111558364; Wed, 03 May 2023 03:59:18 -0700 (PDT) MIME-Version: 1.0 References: <20230426214514.3355280-1-collison@rivosinc.com> <20230426214514.3355280-5-collison@rivosinc.com> In-Reply-To: <20230426214514.3355280-5-collison@rivosinc.com> From: Kito Cheng Date: Wed, 3 May 2023 18:59:07 +0800 Message-ID: Subject: Re: [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks To: Michael Collison Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > @@ -275,6 +284,9 @@ poly_uint16 riscv_vector_chunks; > /* The number of bytes in a vector chunk. */ > unsigned riscv_bytes_per_vector_chunk; > > +/* Prefer vf for auto-vectorizer. */ > +unsigned riscv_vectorization_factor; > + Drop this, we have riscv_autovec_lmul > /* Index R is the smallest register class that contains register R. */ > const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { > GR_REGS, GR_REGS, GR_REGS, GR_REGS, > @@ -6363,6 +6375,9 @@ riscv_option_override (void) > > /* Convert -march to a chunks count. */ > riscv_vector_chunks = riscv_convert_vector_bits (); > + > + if (TARGET_VECTOR) > + riscv_vectorization_factor = RVV_LMUL1; Drop this, we have riscv_autovec_lmul > +/* Implement TARGET_AUTOVECTORIZE_VECTOR_MODES for RVV. */ > +static unsigned int > +riscv_autovectorize_vector_modes (vector_modes *modes, bool) > +{ > + if (!TARGET_VECTOR) > + return 0; > + > + if (riscv_vectorization_factor == RVV_LMUL1) Drop this or check with riscv_autovec_lmul. > + { > + modes->safe_push (VNx16QImode); > + modes->safe_push (VNx8QImode); > + modes->safe_push (VNx4QImode); > + modes->safe_push (VNx2QImode); Modes are not consider different VLEN here, you could ref this patch[1] to see how to get right mode via get_vector_mode [1] https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zhong@rivai.ai/