From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x935.google.com (mail-ua1-x935.google.com [IPv6:2607:f8b0:4864:20::935]) by sourceware.org (Postfix) with ESMTPS id A8B213858439 for ; Tue, 16 May 2023 07:54:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A8B213858439 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x935.google.com with SMTP id a1e0cc1a2514c-77d049b9040so2321667241.1 for ; Tue, 16 May 2023 00:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684223650; x=1686815650; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=pdTHfuDUCC0wDIwJLLDveLwWIINQtDVNsiSwepwQc0k=; b=J5VGOMOrbYbY7cGCq++C09BRbwg2UD5K7M0ev3yn4GMjOEFIqqBcTZt55jJZyu0OB2 p0BuMObKOqey9AnkN/s/Ux3CGVN6ZRVh/2vuRJoa+5ir1kmAexstag249foYMKiU3Pjy lDTaHd4vovlL6H5Uh45JKeGodkT1LzyIim4cusjgP6GCVs0NVpFG56dq9BPTJrQAwvyZ jEQn2ejnSVkR+hDoqw9qQMbA4i1Ou4oLw9fwi5GXecuZls4Y0/0226O85wzmIhl/TmMt OHCM+UBJn9aZ9mxDGI5W9ARIISgUyGpQyp/6pOpPzex/jiZDj1JYUwrz6v+guH1j6w57 Y4gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684223650; x=1686815650; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pdTHfuDUCC0wDIwJLLDveLwWIINQtDVNsiSwepwQc0k=; b=ithrFS/AnWesZoCnNKG5xNSXrFL3gZFGSBIBwpwXdb95YSgLiFgeTT21I73lQRf7VI AoS/vkKXQYAFog7mcmeKyaiGlDbTa/B+228sOydve2syrrIgddXbEBIV+HMXiYRZFnE2 UN960l9DrEjyaETjKx0DRNHJpVHIlRL1pQ1i4mfXUYpQWuFMH3UR4OT+WTGOc66zImEa 0WB+2Xz3cd7BNtw4i4k6RlgjEYWPirwUaGgd8SruieBotvk5dsUv0FzHe3CT06+2DXHG 1qwUcG1CTpFLoDYxjvwyeivWejXB0GCmRmVWK0/4hqWu7lGlacxDDe6CPha7NnoSQ6s/ E8bw== X-Gm-Message-State: AC+VfDzSLWs+IYNdkQGbJeR+9HrE/rW7O2uLFUqcL3jSjiayySzNH85v lA/i2eZ6WxJpjKwRF/1G756q/3DFqrQMmqzz8FA= X-Google-Smtp-Source: ACHHUZ59v8U/vvmTa6a9Fm0zGBFn7Ssdn3QX4NSXcNk+gxGs+cpDccRJZtNL3cI/wAKVk5IXQk9jaPIaBElPbv/7mAE= X-Received: by 2002:a1f:bf49:0:b0:44f:e32a:148 with SMTP id p70-20020a1fbf49000000b0044fe32a0148mr13267994vkf.8.1684223649729; Tue, 16 May 2023 00:54:09 -0700 (PDT) MIME-Version: 1.0 References: <20230419095751.815-1-jinma@linux.alibaba.com> <20230515131628.953-1-jinma@linux.alibaba.com> <8865a17c-54ed-2c4c-cc5b-e3f3baf60a51@gmail.com> In-Reply-To: From: Kito Cheng Date: Tue, 16 May 2023 15:53:58 +0800 Message-ID: Subject: Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2 To: jinma Cc: gcc-patches , Jeff Law , "christoph.muellner" , "kito.cheng" , palmer Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: zfa requires/depend f, it means zfa implies f in current toolchain implementation, could you add that into riscv-common.cc? Also that means zfa is exclusive with Z[FDH]INX. Ref: https://github.com/riscv/riscv-isa-manual/issues/1020 On Tue, May 16, 2023 at 3:06=E2=80=AFPM jinma wro= te: > > On 5/15/23 07:16, Jin Ma wrote: > > > This patch adds the 'Zfa' extension for riscv, which is based on: > > > https://github.com/riscv/riscv-isa-manual/commits/zfb > > > > > > The binutils-gdb for 'Zfa' extension: > > > https://sourceware.org/pipermail/binutils/2023-April/127060.html > > > > > > What needs special explanation is: > > > 1, The immediate number of the instructions FLI.H/S/D is represented = in the assembly as a > > > floating-point value, with scientific counting when rs1 is 2,3, an= d decimal numbers for > > > the rest. > > > > > > Related llvm link: > > > https://reviews.llvm.org/D145645 > > > Related discussion link: > > > https://github.com/riscv/riscv-isa-manual/issues/980 > > > > > > 2, According to riscv-spec, "The FCVTMO D.W.D instruction was added p= rincipally to > > > accelerate the processing of JavaScript Numbers.", so it seems tha= t no implementation > > > is required. > > > > > > 3, The instructions FMINM and FMAXM correspond to C23 library functio= n fminimum and fmaximum. > > > Therefore, this patch has simply implemented the pattern of fminm<= hf\sf\df>3 and > > > fmaxm3 to prepare for later. > > > > > > gcc/ChangeLog: > > > > > > * common/config/riscv/riscv-common.cc: Add zfa extension version. > > > * config/riscv/constraints.md (zfli): Constrain the floating point n= umber that the > > > instructions FLI.H/S/D can load. > > > * config/riscv/iterators.md (ceil): New. > > > (rup): New. > > > * config/riscv/riscv-opts.h (MASK_ZFA): New. > > > (TARGET_ZFA): New. > > > * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli):= New. > > > * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): New. > > > (riscv_cannot_force_const_mem): If instruction FLI.H/S/D can be used= , memory is not applicable. > > > (riscv_const_insns): Likewise. > > > (riscv_legitimize_const_move): Likewise. > > > (riscv_split_64bit_move_p): If instruction FLI.H/S/D can be used, no= split is required. > > > (riscv_split_doubleword_move): Likewise. > > > (riscv_output_move): Output the mov instructions in zfa extension. > > > (riscv_print_operand): Output the floating-point value of the FLI.H/= S/D immediate in assembly > > > (riscv_secondary_memory_needed): Likewise. > > > * config/riscv/riscv.md (fminm3): New. > > > (fmaxm3): New. > > > (movsidf2_low_rv32): New. > > > (movsidf2_high_rv32): New. > > > (movdfsisi3_rv32): New. > > > (f_quiet4_zfa): Likewise. > > > > > > gcc/testsuite/ChangeLog: > > > > > > * gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test. > > > * gcc.target/riscv/zfa-fleq-fltq.c: New test. > > > * gcc.target/riscv/zfa-fli-rv32.c: New test. > > > * gcc.target/riscv/zfa-fli-zfh-rv32.c: New test. > > > * gcc.target/riscv/zfa-fli-zfh.c: New test. > > > * gcc.target/riscv/zfa-fli.c: New test. > > > * gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test. > > > * gcc.target/riscv/zfa-fround-rv32.c: New test. > > > * gcc.target/riscv/zfa-fround.c: New test. > > > --- > > > gcc/common/config/riscv/riscv-common.cc | 4 + > > > gcc/config/riscv/constraints.md | 21 +- > > > gcc/config/riscv/iterators.md | 5 + > > > gcc/config/riscv/riscv-opts.h | 3 + > > > gcc/config/riscv/riscv-protos.h | 1 + > > > gcc/config/riscv/riscv.cc | 204 +++++++++++++++= ++- > > > gcc/config/riscv/riscv.md | 145 +++++++++++-- > > > .../gcc.target/riscv/zfa-fleq-fltq-rv32.c | 19 ++ > > > .../gcc.target/riscv/zfa-fleq-fltq.c | 19 ++ > > > gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c | 79 +++++++ > > > .../gcc.target/riscv/zfa-fli-zfh-rv32.c | 41 ++++ > > > gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c | 41 ++++ > > > gcc/testsuite/gcc.target/riscv/zfa-fli.c | 79 +++++++ > > > .../gcc.target/riscv/zfa-fmovh-fmovp-rv32.c | 10 + > > > .../gcc.target/riscv/zfa-fround-rv32.c | 42 ++++ > > > gcc/testsuite/gcc.target/riscv/zfa-fround.c | 42 ++++ > > > 16 files changed, 719 insertions(+), 36 deletions(-) > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq-rv3= 2.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh-rv32.= c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-r= v32.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround-rv32.c > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c > > > > > > > > > > + > > > +/* Return index of the FLI instruction table if rtx X is an immediat= e constant that can > > > + be moved using a single FLI instruction in zfa extension. Return = -1 if not found. */ > > > + > > > +int > > > +riscv_float_const_rtx_index_for_fli (rtx x) > > > +{ > > > + unsigned HOST_WIDE_INT *fli_value_array; > > > + > > > + machine_mode mode =3D GET_MODE (x); > > > + > > > + if (!TARGET_ZFA > > > + || !CONST_DOUBLE_P(x) > > > + || mode =3D=3D VOIDmode > > > + || (mode =3D=3D HFmode && !TARGET_ZFH) > > > + || (mode =3D=3D SFmode && !TARGET_HARD_FLOAT) > > > + || (mode =3D=3D DFmode && !TARGET_DOUBLE_FLOAT)) > > > + return -1; > > Do we also need to check Z[FDH]INX too? > > > > Otherwise it looks pretty good. We just need to wait for everything to > > freeze and finalization on the assembler interface. > > > > jeff > > Yes, you are right, we also need to check Z[FDH]INX. I will send a patch > again to fix it after others give some review comments. > > Jin