From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2a.google.com (mail-vs1-xe2a.google.com [IPv6:2607:f8b0:4864:20::e2a]) by sourceware.org (Postfix) with ESMTPS id 38161385B533 for ; Thu, 23 Mar 2023 03:27:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 38161385B533 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2a.google.com with SMTP id by13so17882568vsb.3 for ; Wed, 22 Mar 2023 20:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679542072; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=rhX2hLGVyFCf0KmnOhPg5vdELtdUc27IOBQivambHr0=; b=kKffKW/N9Ndouj2B3sTMSvaE2w8Hc3ShxNaE6nyQLmBUOh9FjYzbaZFQf7tIVcz6r9 jQSYI4YRn4VbgT+T7tnpumDP+KM17JyofzPkiybJy2kcOfOc6YOweH3ZL0KxOH0LShrS v/8yEiUestDabKVvmmKEO4WodcvRsU0hSLm8XqkYUIe0QTvKFS6UpN47hdUIG12hU7dM OzdtBE59x5oedVDDdVwtzc64hNN++oexKKJD9vsSQ74y7LtFS3MRSWgvyO5UpD0QtHyw 7Cb8MfdTV6oyQTuV5bZ42trhF2BmdAg63v9tZwOfGcwwvyXmn5WHWgKyJx6Y77PvJCem sEUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679542072; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rhX2hLGVyFCf0KmnOhPg5vdELtdUc27IOBQivambHr0=; b=j7rENAlA1GcrRX21ziPMlz79qokMcKhapPIB7Ikaf08PsncOnNk+zdzpZ8C6zCDr27 EAfS1A9ObJUUejalsa6XqKMAcrjp0T3TlXMYVtwIEu/qBt13v/dUIYmqLlz4YGJhoam/ OVR6SFySY4nla9Ku+Kr8FNT0Ji9dzYUF7aGvE4rkwYaSRU0e/15eNYl29Cab4kQYmI69 CUatntLLGxUqheJk/0QYeIdO8dwEIA/yB8seUzl8/EFnxgqhU1/R6UC20PhH/zj1I/Ps aB462ORYkS7bJ+g5UapOFiBT6YjKJolUJE+eE3ciF9ZslN7tmgqMMjqjV6WuQn5uvycn P2DQ== X-Gm-Message-State: AO0yUKUl0GOucyfjk/Xh7LWf5SPyuvSn6DE60vbxycHZJyqpxhA2pVCC pnuoCs5JUCZjiE5ym3Qrirz3gCDXbU+99Y2rBqk= X-Google-Smtp-Source: AK7set9qlbnwAytPSmZPvWwCKww7cqomWgN0I/h26VVzemp/g+49A/nbOHAxbbTwcbnCJVWMr7rVd/DV9yIwIkyrMZ8= X-Received: by 2002:a67:c806:0:b0:421:eabb:cd6a with SMTP id u6-20020a67c806000000b00421eabbcd6amr1003183vsk.7.1679542072343; Wed, 22 Mar 2023 20:27:52 -0700 (PDT) MIME-Version: 1.0 References: <20230322121556.94496-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230322121556.94496-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 23 Mar 2023 11:27:41 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, but pending this to the GCC 14 queue. On Wed, Mar 22, 2023 at 8:16=E2=80=AFPM wrote: > > From: Ju-Zhe Zhong > > Current expansion of vmsge will make RA produce redundant vmv1r.v. > > testcase: > void f1 (void * in, void *out, int32_t x) > { > vbool32_t mask =3D *(vbool32_t*)in; > asm volatile ("":::"memory"); > vint32m1_t v =3D __riscv_vle32_v_i32m1 (in, 4); > vint32m1_t v2 =3D __riscv_vle32_v_i32m1_m (mask, in, 4); > vbool32_t m3 =3D __riscv_vmsge_vx_i32m1_b32 (v, x, 4); > vbool32_t m4 =3D __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v, x, 4); > m4 =3D __riscv_vmsge_vv_i32m1_b32_m (m4, v2, v2, 4); > __riscv_vsm_v_b32 (out, m4, 4); > } > > Before this patch: > f1: > vsetvli a5,zero,e8,mf4,ta,ma > vlm.v v0,0(a0) > vsetivli zero,4,e32,m1,ta,mu > vle32.v v3,0(a0) > vle32.v v2,0(a0),v0.t > vmslt.vx v1,v3,a2 > vmnot.m v1,v1 > vmslt.vx v1,v3,a2,v0.t > vmxor.mm v1,v1,v0 > vmv1r.v v0,v1 > vmsge.vv v2,v2,v2,v0.t > vsm.v v2,0(a1) > ret > > After this patch: > f1: > vsetvli a5,zero,e8,mf4,ta,ma > vlm.v v0,0(a0) > vsetivli zero,4,e32,m1,ta,mu > vle32.v v3,0(a0) > vle32.v v2,0(a0),v0.t > vmslt.vx v1,v3,a2 > vmnot.m v1,v1 > vmslt.vx v1,v3,a2,v0.t > vmxor.mm v0,v1,v0 > vmsge.vv v2,v2,v2,v0.t > vsm.v v2,0(a1) > ret > > > gcc/ChangeLog: > > * config/riscv/vector.md: Fix redundant vmv1r.v. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/binop_vx_constraint-150.c: Adapt asse= mbly check. > > --- > gcc/config/riscv/vector.md | 15 +++++++-------- > .../riscv/rvv/base/binop_vx_constraint-150.c | 2 +- > 2 files changed, 8 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index ebb014aecb1..f06d68be80f 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -4111,6 +4111,7 @@ > { > enum rtx_code code =3D GET_CODE (operands[3]); > rtx undef =3D RVV_VUNDEF (mode); > + rtx tmp =3D gen_reg_rtx (mode); > if (code =3D=3D GEU && rtx_equal_p (operands[5], const0_rtx)) > { > /* If vmsgeu with 0 immediate, expand it to vmset. */ > @@ -4157,12 +4158,11 @@ > - pseudoinstruction: vmsge{u}.vx vd, va, x > - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */ > emit_insn ( > - gen_pred_cmp_scalar (operands[0], operands[1], operands= [2], > + gen_pred_cmp_scalar (tmp, operands[1], operands[2], > operands[3], operands[4], operand= s[5], > operands[6], operands[7], operand= s[8])); > emit_insn (gen_pred_nand (operands[0], CONSTM1_RTX (mod= e), > - undef, operands[0], operands[0], > - operands[6], operands[8])); > + undef, tmp, tmp, operands[6], ope= rands[8])); > } > else > { > @@ -4171,13 +4171,12 @@ > /* masked va >=3D x, vd =3D=3D v0 > - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt > - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt= . */ > - rtx reg =3D gen_reg_rtx (mode); > emit_insn (gen_pred_cmp_scalar ( > - reg, CONSTM1_RTX (mode), undef, operands[3], operands= [4], > + tmp, CONSTM1_RTX (mode), undef, operands[3], operands= [4], > operands[5], operands[6], operands[7], operands[8])); > emit_insn ( > gen_pred_andnot (operands[0], CONSTM1_RTX (mode),= undef, > - operands[1], reg, operands[6], operand= s[8])); > + operands[1], tmp, operands[6], operand= s[8])); > } > else > { > @@ -4186,10 +4185,10 @@ > - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd= , v0. > */ > emit_insn (gen_pred_cmp_scalar ( > - operands[0], operands[1], operands[2], operands[3], opera= nds[4], > + tmp, operands[1], operands[2], operands[3], operands[4], > operands[5], operands[6], operands[7], operands[8])); > emit_insn (gen_pred (XOR, mode, operands[0], > - CONSTM1_RTX (mode), undef, operand= s[0], > + CONSTM1_RTX (mode), undef, tmp, > operands[1], operands[6], operands[8])= ); > } > } > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-= 150.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c > index 55a222f47ea..e92a8115f09 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c > @@ -18,4 +18,4 @@ void f1 (void * in, void *out, int32_t x) > /* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*= [a-x0-9]+,\s*v0.t} 1 } } */ > /* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*= v[0-9]+} 1 } } */ > /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 }= } */ > -/* { dg-final { scan-assembler-times {vmv} 1 } } */ > +/* { dg-final { scan-assembler-not {vmv} } } */ > -- > 2.36.1 >