From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 815403858010 for ; Fri, 28 Oct 2022 09:37:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 815403858010 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62c.google.com with SMTP id sc25so11582481ejc.12 for ; Fri, 28 Oct 2022 02:37:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=gm2XLKFFxY4XSWnVMqJPta2fZWHLNPAuSq7lWvHckxk=; b=QQ8Ap9N6JERH2r4vZw04/TakhSKZwGmiCS5zF+gVRlor4shw5RgxY8PAoClJUM+TUv PxgMX1pX8cnO8Yv93BTRyHa328KqIcm80sdpVftxpji9wb9MPbssCtfITnQKGjQiGrkP uFawbIoqQjp+p+6bab244C3I2jIvzYFUsxKk4eIgGPIhTV9hjKiac2X0RAfcerbLhR9r /4asb3v6sqNbfp/m+r+TjBwU3Wo5Y0/32QfgDKO1e7sHjA/uEo82QK82rkfLlIyIefwA CcJyPvoHXst2M/CdVQJrQRYfE8YNDzqmn+2UxECvIc3mkwZLMt9FpuORxo5YwhJrZQ+O W+Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gm2XLKFFxY4XSWnVMqJPta2fZWHLNPAuSq7lWvHckxk=; b=dygV0FSCRpk2q2sqYF6qWHctVodqGcvWwz0oOSNfvVo6G4QIUpqX0DZI/n4GgzmkoG j6nwMwxLseOWFI3uzXidJR6FhLu/ROxWBmMTRaDsqWJR2AeV6RJUwIlx7ihTPlq0dqXp 2LcafFeswGyMJ/attk4UTvrmqEEn6jYu+laI/xgMJjSMKus84pK5yIlwl3s+6D40t3ma dnxuY+mgKFPkD875c9O8WTfMX+JPRqhSQVBn2xxMYENDXC4p3G9dD10dDrnYhSyjmyAU QyaZuURbsgUg9k131scAlEm326qgV6skmzRDbzaxO4DOujUHYf7YcPYPqvGv8UPS4nPg lbbg== X-Gm-Message-State: ACrzQf1g/PMnbyNntr4yVCOyd9o6gL/CZVo7HdHZRkEfxJGhW2kbxQYl xiffGFRNrV/nxhWfNWG21Nfn8oKGjuBOAfoZTZ0= X-Google-Smtp-Source: AMsMyM7+Yri0Q1onq+ptmMJc/bLW4iwGDG3wPTaScA7wSmRR0Kx4FD6iiHIJ0qbd8tjqysxD69lUNJtg4XbL9V6nX0o= X-Received: by 2002:a17:906:8a47:b0:7a3:86dd:d33b with SMTP id gx7-20020a1709068a4700b007a386ddd33bmr27496902ejc.67.1666949846033; Fri, 28 Oct 2022 02:37:26 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Kito Cheng Date: Fri, 28 Oct 2022 17:37:13 +0800 Message-ID: Subject: Re: [PATCH v3] RISC-V: Libitm add RISC-V support. To: Xiongchuan Tan Cc: gcc-patches@gcc.gnu.org, fantasquex@gmail.com, Andrew Waterman Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I guess we don't really care about RV32E here, but in case you add a guard for that? #ifdef __riscv_e #error "rv32e unsupported" #endif On Fri, Oct 28, 2022 at 4:39 PM Xiongchuan Tan via Gcc-patches wrote: > > Reviewed-by: Palmer Dabbelt > Acked-by: Palmer Dabbelt > > libitm/ChangeLog: > > * configure.tgt: Add riscv support. > * config/riscv/asm.h: New file. > * config/riscv/sjlj.S: New file. > * config/riscv/target.h: New file. > --- > v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see > https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) > > v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in > cpu_relax() > > libitm/config/riscv/asm.h | 54 +++++++++++++ > libitm/config/riscv/sjlj.S | 144 +++++++++++++++++++++++++++++++++++ > libitm/config/riscv/target.h | 62 +++++++++++++++ > libitm/configure.tgt | 2 + > 4 files changed, 262 insertions(+) > create mode 100644 libitm/config/riscv/asm.h > create mode 100644 libitm/config/riscv/sjlj.S > create mode 100644 libitm/config/riscv/target.h > > diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h > new file mode 100644 > index 0000000..bb515f2 > --- /dev/null > +++ b/libitm/config/riscv/asm.h > @@ -0,0 +1,54 @@ > +/* Copyright (C) 2022 Free Software Foundation, Inc. > + Contributed by Xiongchuan Tan . > + > + This file is part of the GNU Transactional Memory Library (libitm). > + > + Libitm is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3 of the License, or > + (at your option) any later version. > + > + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY > + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS > + FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + more details. > + > + Under Section 7 of GPL version 3, you are granted additional > + permissions described in the GCC Runtime Library Exception, version > + 3.1, as published by the Free Software Foundation. > + > + You should have received a copy of the GNU General Public License and > + a copy of the GCC Runtime Library Exception along with this program; > + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > + . */ > + > +#ifndef _RV_ASM_H > +#define _RV_ASM_H > + > +#if __riscv_xlen == 64 > +# define GPR_L ld > +# define GPR_S sd > +# define SZ_GPR 8 > +# define LEN_GPR 14 > +#elif __riscv_xlen == 32 > +# define GPR_L lw > +# define GPR_S sw > +# define SZ_GPR 4 > +# define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */ > +#else > +# error Unsupported XLEN (must be 64-bit or 32-bit). > +#endif > + > +#if defined(__riscv_flen) && __riscv_flen == 64 > +# define FPR_L fld > +# define FPR_S fsd > +# define SZ_FPR 8 > +#elif defined(__riscv_flen) && __riscv_flen == 32 > +# define FPR_L flw > +# define FPR_S fsw > +# define SZ_FPR 4 Check __riscv_flen is not 32 or 64 here, in case we add Q-extension then we can error out. > diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S > new file mode 100644 > index 0000000..93f12ec > --- /dev/null > +++ b/libitm/config/riscv/sjlj.S > @@ -0,0 +1,144 @@ > +#include "asmcfi.h" > +#include "asm.h" > + > + .text > + .align 2 > + .global _ITM_beginTransaction > + .type _ITM_beginTransaction, @function > + > +_ITM_beginTransaction: > + cfi_startproc > + mv a1, sp > + addi sp, sp, -(LEN_GPR*SZ_GPR+ 12*SZ_FPR) This expression appeared 4 times, maybe define a marco ADJ_STACK_SIZE or something else to hold that? > + cfi_adjust_cfa_offset(LEN_GPR*SZ_GPR+ 12*SZ_FPR) > diff --git a/libitm/config/riscv/target.h b/libitm/config/riscv/target.h > new file mode 100644 > index 0000000..b8a1665 > --- /dev/null > +++ b/libitm/config/riscv/target.h > @@ -0,0 +1,62 @@ > +typedef struct gtm_jmpbuf > + { > + long int pc; > + void *cfa; > + long int s[12]; /* Saved registers, s0 is fp */ > + > +#if __riscv_xlen == 32 > + /* Ensure that the stack is 16-byte aligned */ > + long int padding[2]; > +#endif > + > + /* FP saved registers */ > +#if defined(__riscv_flen) && __riscv_flen == 64 > + double fs[12]; > +#elif defined(__riscv_flen) && __riscv_flen == 32 > + float fs[12]; Same here, error __riscv_flen if defined but not 64 or 32.