Re: [PATCH] RISC-V: Recognized Svinval and Svnapot extensions

[Kito Cheng <kito.cheng@gmail.com>]

On Tue, Oct 25, 2022 at 9:37 PM Bernhard Reutner-Fischer via
Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> On 25 October 2022 08:17:33 CEST, Monk Chiang <monk.chiang@sifive.com> wrote:
> >gcc/ChangeLog:
> >
>
> >diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> >index 55e0bc0a0e9..63ac56a8ca0 100644
> >--- a/gcc/config/riscv/riscv-opts.h
> >+++ b/gcc/config/riscv/riscv-opts.h
> >@@ -162,6 +162,12 @@ enum stack_protector_guard {
> > #define MASK_ZMMUL      (1 << 0)
> > #define TARGET_ZMMUL    ((riscv_zm_subext & MASK_ZMMUL) != 0)
> >
> >+#define MASK_SVINVAL (1 << 0)
> >+#define MASK_SVNAPOT (1 << 1)
> >+
> >+#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
> >+#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
> >+
> > /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> >    set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
> >    popcount to caclulate the minimal VLEN.  */
>
> Preexisting, but the above is hard to parse. contintuly, caclulate, will set, has set ?

Thanks for pointing this out, will prepare a patch to improve that later  :)


>
> thanks,