From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe30.google.com (mail-vs1-xe30.google.com [IPv6:2607:f8b0:4864:20::e30]) by sourceware.org (Postfix) with ESMTPS id 61A5F385828E for ; Fri, 3 Feb 2023 07:16:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 61A5F385828E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe30.google.com with SMTP id 187so4449992vsv.10 for ; Thu, 02 Feb 2023 23:16:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=X3hitER0J8qY/2GUSgJYvUTcFDsgBBPoDEOFJWismtw=; b=fWwnRcR7i7uCyG6wVQskodU0kOCjlOn+ifh3wOnuWcEHuhSacQDxuPArbDQsICKi3Q 5V6S41Rrh2eN3VF+uCZAab402YIk6B95CJEr3BW9KOryPXzP+1wk5u4Ma7YNl2RuJZMn 0OOD9EQChE09gEsh7v7vBxN1qkLRoLa5WxpThEJ7RSlqZ33duqY/4ZlKJ0m0ktQSiNlo rs2AZn/ps6v3sysbndACWZGdSTtqzeNebd+50rPLMf7S4UrKg8jp8e0gn7nrINnw3PJU UvbBazW0p1iC/pzayIZyZbmmDlk7brm+A3SlrkENhImGJaIIYA4XXo7cOXCAdRCKHVv2 q+rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=X3hitER0J8qY/2GUSgJYvUTcFDsgBBPoDEOFJWismtw=; b=QeIsMetnvSM08C5GJn4bIn6VxmPdIHCKImTBeeZzVehliW+tmRNapblXInuAxMxAOT Rvbm4VZmL6jcm/PxOfnFxoXbP2EYT3YtWWu7caESqIlx/NRdmEsMGrqH8ZxPW/qojkMM 0s82RgW+xWxGueXhXy/70bf27sJ5lc/brLP43F5Ri8ZaCXCNFR/KcYE4bhcvQRezqvaQ C4cl+hRcuAJEfkKAnY11kHwO+wEwCmUg1P/3IGGQ3jpaBWQX04vp6KT7o/DvNOqloJ/g XePJHe6LDBx6/Z3TPQqLCTl6lCaLpFea0lLUuEQb5+IIppC2S87t1QeXmtdgNWdSpQZM oxag== X-Gm-Message-State: AO0yUKWHefqyQH1yvNyDjHC7e/VYc5nVryZWIkOhDeaTZ4hSs23D18rn 1UXuSS+gGxcycDmGeRWQD5lmzfTswsVaJIYLPwaQpny86bg= X-Google-Smtp-Source: AK7set9hi+OdFKLxSl8CGMxTnPuh0MsKc1DYTbvvvUr0nyFw5R4K6g7aMxdeUB1IVbycPdaVfl6dWx6flshRCNpO0RE= X-Received: by 2002:a67:ad14:0:b0:3d3:e345:ca85 with SMTP id t20-20020a67ad14000000b003d3e345ca85mr1221558vsl.40.1675408610505; Thu, 02 Feb 2023 23:16:50 -0800 (PST) MIME-Version: 1.0 References: <20230131221513.22652-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230131221513.22652-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 3 Feb 2023 15:16:39 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add shift constraint tests To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed, thanks! On Wed, Feb 1, 2023 at 6:15 AM wrote: > > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test. > > --- > .../riscv/rvv/base/shift_vx_constraint-1.c | 133 ++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c > new file mode 100644 > index 00000000000..ae3883c5af9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c > @@ -0,0 +1,133 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > +#include "riscv_vector.h" > + > +/* > +** f1: > +** vsetivli\tzero,4,e32,m1,tu,ma > +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,31 > +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,31 > +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f1 (void * in, void *out) > +{ > + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); > + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); > + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 31, 4); > + vint32m1_t v4 = __riscv_vsll_vx_i32m1_tu (v3, v2, 31, 4); > + __riscv_vse32_v_i32m1 (out, v4, 4); > +} > + > +/* > +** f2: > +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** ... > +** vsetivli\tzero,4,e32,m1,ta,ma > +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ > +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t > +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f2 (void * in, void *out) > +{ > + vbool32_t mask = *(vbool32_t*)in; > + asm volatile ("":::"memory"); > + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); > + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); > + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 32, 4); > + vint32m1_t v4 = __riscv_vsll_vx_i32m1_m (mask, v3, 32, 4); > + __riscv_vse32_v_i32m1 (out, v4, 4); > +} > + > +/* > +** f3: > +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetivli\tzero,4,e32,m1,tu,mu > +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17 > +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17,\s*v0.t > +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f3 (void * in, void *out) > +{ > + vbool32_t mask = *(vbool32_t*)in; > + asm volatile ("":::"memory"); > + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); > + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); > + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 17, 4); > + vint32m1_t v4 = __riscv_vsll_vx_i32m1_tumu (mask, v3, v2, 17, 4); > + __riscv_vse32_v_i32m1 (out, v4, 4); > +} > + > +/* > +** f4: > +** vsetivli\tzero,4,e8,mf8,tu,ma > +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ > +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ > +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f4 (void * in, void *out, size_t x) > +{ > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); > + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4); > + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tu (v3, v2, x, 4); > + __riscv_vse8_v_i8mf8 (out, v4, 4); > +} > + > +/* > +** f5: > +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetivli\tzero,4,e8,mf8,ta,ma > +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5 > +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5,\s*v0.t > +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f5 (void * in, void *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); > + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, 5, 4); > + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_m (mask, v3, 5, 4); > + __riscv_vse8_v_i8mf8 (out, v4, 4); > +} > + > +/* > +** f6: > +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetivli\tzero,4,e8,mf8,tu,mu > +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ > +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t > +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f6 (void * in, void *out, size_t x) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); > + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4); > + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tumu (mask, v3, v2, x, 4); > + __riscv_vse8_v_i8mf8 (out, v4, 4); > +} > -- > 2.36.3 >